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authorNico Rikken <nico@nicorikken.eu>2018-01-30 19:00:45 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-04-06 07:08:27 +0000
commitecea3d450c12062a341415e5bea92f67019b036c (patch)
tree1405a01c4c3de8f1c85c9874087653ad542a7c1d /src/mainboard/lenovo/t520
parent3f7de0686d79836d1f62b3d6399e7bcde78d7a27 (diff)
downloadcoreboot-ecea3d450c12062a341415e5bea92f67019b036c.tar.xz
mb/lenovo/w520: Add ThinkPad W520 support
Tested and working: * 4 RAM-slots * Speakers * PCIe Wifi * Camera * Fan * Touchpad, trackpoint and keyboard * Ethernet * Keyboard ACPI events * USB 3.0 * SD-card reader * Native graphics (LCD panel) * Harddisk in Ultrabay * SeaBIOS payloads ** Debian Live ** Debian testing 4.14.0-3-amd64 * GRUB ** Debian Live ** Debian testing 4.14.0-3-amd64 Not working: * Displayport and VGA output (requires VGA option ROM and ACPI switch call) Not tested: * Intel VGA option ROM * ACPI events related to ultrabay * Smart card reader * Docking station Change-Id: I1deb0436a807950c605dcd590deedcb3169bf8c5 Signed-off-by: Nico Rikken <nico@nicorikken.eu> Reviewed-on: https://review.coreboot.org/23564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/lenovo/t520')
-rw-r--r--src/mainboard/lenovo/t520/Kconfig23
-rw-r--r--src/mainboard/lenovo/t520/Kconfig.name5
-rw-r--r--src/mainboard/lenovo/t520/Makefile.inc3
-rw-r--r--src/mainboard/lenovo/t520/board_info.txt4
-rw-r--r--src/mainboard/lenovo/t520/romstage.c7
-rw-r--r--src/mainboard/lenovo/t520/variants/t520/board_info.txt8
-rw-r--r--src/mainboard/lenovo/t520/variants/t520/devicetree.cb (renamed from src/mainboard/lenovo/t520/devicetree.cb)0
-rw-r--r--src/mainboard/lenovo/t520/variants/t520/gpio.c (renamed from src/mainboard/lenovo/t520/gpio.c)0
-rw-r--r--src/mainboard/lenovo/t520/variants/t520/romstage.c24
-rw-r--r--src/mainboard/lenovo/t520/variants/w520/board_info.txt8
-rw-r--r--src/mainboard/lenovo/t520/variants/w520/devicetree.cb168
-rw-r--r--src/mainboard/lenovo/t520/variants/w520/gpio.c221
-rw-r--r--src/mainboard/lenovo/t520/variants/w520/romstage.c26
13 files changed, 483 insertions, 14 deletions
diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig
index 8c19c625e0..2adfa33fda 100644
--- a/src/mainboard/lenovo/t520/Kconfig
+++ b/src/mainboard/lenovo/t520/Kconfig
@@ -1,7 +1,5 @@
-if BOARD_LENOVO_T520
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
+config BOARD_LENOVO_BASEBOARD_T520
+ def_bool n
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA988B
select NORTHBRIDGE_INTEL_SANDYBRIDGE
@@ -23,6 +21,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE
+if BOARD_LENOVO_BASEBOARD_T520
+
config HAVE_IFD_BIN
bool
default n
@@ -31,13 +31,24 @@ config HAVE_ME_BIN
bool
default n
+config VARIANT_DIR
+ string
+ default "t520" if BOARD_LENOVO_T520
+ default "w520" if BOARD_LENOVO_W520
+
config MAINBOARD_DIR
string
default lenovo/t520
+config DEVICETREE
+ string
+ default "variants/t520/devicetree.cb" if BOARD_LENOVO_T520
+ default "variants/w520/devicetree.cb" if BOARD_LENOVO_W520
+
config MAINBOARD_PART_NUMBER
string
- default "ThinkPad T520"
+ default "ThinkPad T520" if BOARD_LENOVO_T520
+ default "ThinkPad W520" if BOARD_LENOVO_W520
config MAX_CPUS
int
@@ -71,4 +82,4 @@ config ONBOARD_VGA_IS_PRIMARY
bool
default y
-endif # BOARD_LENOVO_T520
+endif
diff --git a/src/mainboard/lenovo/t520/Kconfig.name b/src/mainboard/lenovo/t520/Kconfig.name
index c1b1bff599..cc622f049a 100644
--- a/src/mainboard/lenovo/t520/Kconfig.name
+++ b/src/mainboard/lenovo/t520/Kconfig.name
@@ -1,2 +1,7 @@
config BOARD_LENOVO_T520
bool "ThinkPad T520"
+ select BOARD_LENOVO_BASEBOARD_T520
+
+config BOARD_LENOVO_W520
+ bool "ThinkPad W520"
+ select BOARD_LENOVO_BASEBOARD_T520
diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc
index 9eb141adc9..5c450ebd33 100644
--- a/src/mainboard/lenovo/t520/Makefile.inc
+++ b/src/mainboard/lenovo/t520/Makefile.inc
@@ -14,4 +14,5 @@
##
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-romstage-y += gpio.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
diff --git a/src/mainboard/lenovo/t520/board_info.txt b/src/mainboard/lenovo/t520/board_info.txt
index c2ee633abd..3265241c98 100644
--- a/src/mainboard/lenovo/t520/board_info.txt
+++ b/src/mainboard/lenovo/t520/board_info.txt
@@ -1,6 +1,8 @@
+Vendor name: Lenovo
+Board name: ThinkPad T520 baseboard
Category: laptop
ROM package: WSON-8
ROM protocol: SPI
ROM socketed: n
-Flashrom support: n
+Flashrom support: y
Release year: 2011
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index 304f337e81..638e7ca67b 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -84,7 +84,7 @@ void mainboard_rcba_config(void)
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 }, /* P0 left dual conn, OC 0 */
- { 1, 1, 1 }, /* P1 system onboard USB port (eSATA), (EHCI debug), OC 1 */
+ { 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */
{ 1, 2, -1 }, /* P2: wimax / WLAN */
{ 1, 1, -1 }, /* P3: WWAN, no OC */
{ 1, 1, -1 }, /* P4: smartcard, no OC */
@@ -99,11 +99,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, -1 }, /* P13: CAMERA (LCD), no OC */
};
-void mainboard_get_spd(spd_raw_data *spd, bool id_only) {
- read_spd (&spd[0], 0x50, id_only);
- read_spd (&spd[2], 0x51, id_only);
-}
-
void mainboard_early_init(int s3resume)
{
hybrid_graphics_init();
diff --git a/src/mainboard/lenovo/t520/variants/t520/board_info.txt b/src/mainboard/lenovo/t520/variants/t520/board_info.txt
new file mode 100644
index 0000000000..64768dc50c
--- /dev/null
+++ b/src/mainboard/lenovo/t520/variants/t520/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: Lenovo
+Board name: ThinkPad T520
+Category: laptop
+ROM package: WSON-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb
index f03b87e6c0..f03b87e6c0 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb
diff --git a/src/mainboard/lenovo/t520/gpio.c b/src/mainboard/lenovo/t520/variants/t520/gpio.c
index 54f53cf18b..54f53cf18b 100644
--- a/src/mainboard/lenovo/t520/gpio.c
+++ b/src/mainboard/lenovo/t520/variants/t520/gpio.c
diff --git a/src/mainboard/lenovo/t520/variants/t520/romstage.c b/src/mainboard/lenovo/t520/variants/t520/romstage.c
new file mode 100644
index 0000000000..6db4d6913d
--- /dev/null
+++ b/src/mainboard/lenovo/t520/variants/t520/romstage.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x51, id_only);
+}
diff --git a/src/mainboard/lenovo/t520/variants/w520/board_info.txt b/src/mainboard/lenovo/t520/variants/w520/board_info.txt
new file mode 100644
index 0000000000..d0b6ba0f44
--- /dev/null
+++ b/src/mainboard/lenovo/t520/variants/w520/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: Lenovo
+Board name: ThinkPad W520
+Category: laptop
+ROM package: WSON-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb
new file mode 100644
index 0000000000..b69b66c2fa
--- /dev/null
+++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb
@@ -0,0 +1,168 @@
+chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+
+ # Enable DisplayPort Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Enable Panel as LVDS and configure power delays
+ register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_power_cycle_delay" = "5"
+ register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms
+ register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms
+ register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
+ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gpu_cpu_backlight" = "0x1155"
+ register "gpu_pch_backlight" = "0x06100610"
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_rPGA988B
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
+ end
+ end
+
+ register "pci_mmio_size" = "2048"
+
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M]
+ device pci 02.0 on end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "alt_gp_smi_en" = "0x0000"
+ register "gpi1_routing" = "2"
+ register "gpi13_routing" = "2"
+
+ # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock)
+ register "sata_port_map" = "0x1f"
+ # Set max SATA speed to 6.0 Gb/s
+ register "sata_interface_speed_support" = "0x3"
+
+ register "gen1_dec" = "0x7c1601"
+ register "gen2_dec" = "0x0c15e1"
+ register "gen4_dec" = "0x0c06a1"
+
+ # Enable zero-based linear PCIe root port functions
+ register "pcie_port_coalesce" = "1"
+
+ register "c2_latency" = "101" # c2 not supported
+ register "p_cnt_throttling_supported" = "1"
+
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+
+ register "spi_uvscc" = "0x2005"
+ register "spi_lvscc" = "0x2005"
+
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end
+ device pci 16.2 off end
+ device pci 16.3 off end
+ device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 off end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 on end # PCIe Port #4 Express Card
+ device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394
+ device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY
+ device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1f.0 on #LPC bridge
+ chip ec/lenovo/pmh7
+ device pnp ff.1 on # dummy
+ end
+ register "backlight_enable" = "0x01"
+ register "dock_event_enable" = "0x01"
+ end
+
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+
+ chip ec/lenovo/h8
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+
+ register "config0" = "0xa7"
+ register "config1" = "0x09"
+ register "config2" = "0xa0"
+ register "config3" = "0xc2"
+
+ register "beepmask0" = "0x00"
+ register "beepmask1" = "0x86"
+ register "has_power_management_beeps" = "0"
+ register "event2_enable" = "0xff"
+ register "event3_enable" = "0xff"
+ register "event4_enable" = "0xd0"
+ register "event5_enable" = "0xfc"
+ register "event6_enable" = "0x00"
+ register "event7_enable" = "0x01"
+ register "event8_enable" = "0x7b"
+ register "event9_enable" = "0xff"
+ register "eventa_enable" = "0x01"
+ register "eventb_enable" = "0x00"
+ register "eventc_enable" = "0xff"
+ register "eventd_enable" = "0xff"
+ register "evente_enable" = "0x0d"
+
+ register "has_bdc_detection" = "1"
+ register "bdc_gpio_num" = "54"
+ register "bdc_gpio_lvl" = "0"
+ end
+ chip drivers/lenovo/hybrid_graphics
+ device pnp ff.f on end # dummy
+
+ register "detect_gpio" = "21"
+
+ register "has_panel_hybrid_gpio" = "1"
+ register "panel_hybrid_gpio" = "52"
+ register "panel_integrated_lvl" = "1"
+
+ register "has_backlight_gpio" = "0"
+ register "has_dgpu_power_gpio" = "0"
+
+ register "has_thinker1" = "1"
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on # SMBUS controller
+ # eeprom, 8 virtual devices, same chip
+ chip drivers/i2c/at24rf08c
+ device i2c 54 on end
+ device i2c 55 on end
+ device i2c 56 on end
+ device i2c 57 on end
+ device i2c 5c on end
+ device i2c 5d on end
+ device i2c 5e on end
+ device i2c 5f on end
+ end
+ end # SMBus
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/t520/variants/w520/gpio.c b/src/mainboard/lenovo/t520/variants/w520/gpio.c
new file mode 100644
index 0000000000..9d9a83a1fe
--- /dev/null
+++ b/src/mainboard/lenovo/t520/variants/w520/gpio.c
@@ -0,0 +1,221 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio10 = GPIO_LEVEL_HIGH,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio1 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_GPIO,
+ .gpio42 = GPIO_MODE_GPIO,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio41 = GPIO_DIR_OUTPUT,
+ .gpio42 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio41 = GPIO_LEVEL_HIGH,
+ .gpio42 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_HIGH,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio55 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/lenovo/t520/variants/w520/romstage.c b/src/mainboard/lenovo/t520/variants/w520/romstage.c
new file mode 100644
index 0000000000..aeee54a208
--- /dev/null
+++ b/src/mainboard/lenovo/t520/variants/w520/romstage.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x52, id_only);
+ read_spd(&spd[2], 0x51, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}