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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-09-05 16:29:41 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-10-16 14:46:55 +0200 |
| commit | 332f14b60b241d1793401ea50b22785ad81c97cd (patch) | |
| tree | 3b92dfc8af555c75228fd620b887f3b4d72299a1 /src/mainboard/lenovo/t520 | |
| parent | c845b43f0a404adaf96808a122c591c5552dc818 (diff) | |
| download | coreboot-332f14b60b241d1793401ea50b22785ad81c97cd.tar.xz | |
bd82x6x: Move common bd82x6x S3 detect to bd82x6x code.
Change-Id: I9ba1fa5f9ad38cb619466c6199eacd219bc53281
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6921
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/lenovo/t520')
| -rw-r--r-- | src/mainboard/lenovo/t520/romstage.c | 21 |
1 files changed, 1 insertions, 20 deletions
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 8fc0f5f037..a0cbad5ac7 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -114,8 +114,6 @@ void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; if (MCHBAR16(SSKPD) == 0xCAFE) { outb(0x6, 0xcf9); @@ -196,24 +194,7 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } + boot_mode = southbridge_detect_s3_resume() ? 2 : 0; post_code(0x38); /* Enable SPD ROMs and DDR-III DRAM */ |