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| author | Nicolas Reinecke <nr@das-labor.org> | 2015-02-01 02:53:35 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-03-10 23:53:17 +0100 |
| commit | b0922f0183cb50b9714285c539c387956d86814c (patch) | |
| tree | 95d390fda6c2e8e0c95afc983c52284e33417b12 /src/mainboard/lenovo/t520 | |
| parent | 60ef456f46d81faa4f15b8a49b39037037b8b643 (diff) | |
| download | coreboot-b0922f0183cb50b9714285c539c387956d86814c.tar.xz | |
lenovo: fix smi gpe + wakeup pin for t420s t520 t530 x220 x230
Set correct gpio routing and enable bits for EC SMI gpio and EC WAKE gpio.
Verified with schematics.
Change-Id: Ie3b98c4456a870c881e7663b19eb8ca8e5564c5c
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8358
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/t520')
| -rw-r--r-- | src/mainboard/lenovo/t520/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t520/smihandler.c | 19 |
2 files changed, 12 insertions, 9 deletions
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index d2a4d6b9b7..bf575d8da1 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -50,7 +50,7 @@ chip northbridge/intel/sandybridge # 2 SCI (if corresponding GPIO_EN bit is also set) register "alt_gp_smi_en" = "0x0000" register "gpi1_routing" = "2" - register "gpi8_routing" = "2" + register "gpi13_routing" = "2" # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) register "sata_port_map" = "0x1f" diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index bb3ad783bd..479ce0a8e4 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -33,6 +33,9 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -103,7 +106,7 @@ static void mainboard_smi_handle_ec_sci(void) void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << 12)) + if (gpi_sts & (1 << GPE_EC_SCI)) mainboard_smi_handle_ec_sci(); } @@ -124,8 +127,8 @@ int mainboard_smi_apmc(u8 data) case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); - /* route H8SCI to SCI */ - outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + /* route EC_SCI to SCI */ + outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; @@ -137,8 +140,8 @@ int mainboard_smi_apmc(u8 data) /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); - /* route H8SCI# to SMI */ - outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, + /* route EC_SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; @@ -178,11 +181,11 @@ void mainboard_smi_sleep(u8 slp_typ) u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; /* Enable EC WAKE GPE. */ - outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN); gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); /* Redirect EC WAKE GPE to SCI. */ - gpe_rout &= ~(3 << 26); - gpe_rout |= (2 << 26); + gpe_rout &= ~(3 << (GPE_EC_WAKE * 2)); + gpe_rout |= (2 << (GPE_EC_WAKE * 2)); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); } } |