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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-07-29 14:42:26 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-09-12 19:20:33 +0200 |
| commit | 5fcae806531a0c4a9a8216c2a1a16d326eb2a1db (patch) | |
| tree | 5d42374f3f7dc3ee10abbab2ad171e9c062ebba3 /src/mainboard/lenovo/t530 | |
| parent | 1633261979a9cdec4e6b0ebeb12dac361d3cd8a4 (diff) | |
| download | coreboot-5fcae806531a0c4a9a8216c2a1a16d326eb2a1db.tar.xz | |
lenovo/t530: Use native LVDS gfx init
As introduced in:
1783a3c ivybridge: LVDS gfx init.
The panel on the T530 is a AUO B156HW01 V.4, 40 pin LVDS (2 ch, 6-bit).
Tx parameters derived from datasheet table.
Change-Id: I2e3b56a2a3d1ede08a704b839cc11fe6d685cf5b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6395
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/t530')
| -rw-r--r-- | src/mainboard/lenovo/t530/Kconfig | 6 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t530/devicetree.cb | 10 |
2 files changed, 14 insertions, 2 deletions
diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 8e49277db3..c34b647634 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -14,6 +14,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select INTEL_INT15 + select EARLY_CBMEM_INIT + select VGA + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select IVYBRIDGE_LVDS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 6a09004466..b22d405101 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -8,8 +8,14 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms - register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms + register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms + register "gpu_use_spread_spectrum_clock" = "1" + register "gpu_lvds_dual_channel" = "1" + register "gpu_link_frequency_270_mhz" = "1" + register "gpu_lvds_num_lanes" = "1" + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x11551155" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 |