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authorArthur Heymans <arthur@aheymans.xyz>2018-06-15 22:02:28 +0200
committerFelix Held <felix-coreboot@felixheld.de>2018-11-12 14:06:37 +0000
commitb9d2589ca40026b543ecb5b008ce0d1bc346bf53 (patch)
tree87cac45cfc1c1211f012aaa76b8a87162f092aff /src/mainboard/lenovo/t60
parent81dd52b7eb663c6098de5d8c7c56ed572c91b539 (diff)
downloadcoreboot-b9d2589ca40026b543ecb5b008ce0d1bc346bf53.tar.xz
mb/*/*: Harmonise FD and devicetree on boards featuring ICH7
On some boards the devicetree and Function Disable register did not match. In this case the FD values are put in the devicetree as these were the values that were actually used in practice. A complete devicetree will make it easier to automatically disable devices in ramstage. Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/lenovo/t60')
-rw-r--r--src/mainboard/lenovo/t60/devicetree.cb7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
index 053b9d30cb..7b1721e563 100644
--- a/src/mainboard/lenovo/t60/devicetree.cb
+++ b/src/mainboard/lenovo/t60/devicetree.cb
@@ -90,6 +90,11 @@ chip northbridge/intel/i945
subsystemid 0x17aa 0x2001
end
device pci 1c.1 on end # WLAN
+ device pci 1c.2 on end # PCIe port 3
+ device pci 1c.3 on end # PCIe port 4
+ device pci 1c.4 off end # PCIe port 5
+ device pci 1c.5 off end # PCIe port 6
+
device pci 1d.0 on # USB UHCI
subsystemid 0x17aa 0x200a
end
@@ -115,6 +120,8 @@ chip northbridge/intel/i945
end
end
+ device pci 1e.2 off end # AC'97 Audio
+ device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # PCI-LPC bridge
subsystemid 0x17aa 0x2009
chip ec/lenovo/pmh7