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author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-15 18:26:05 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-19 05:40:16 +0000 |
commit | a1e46aea79a7d51e006d91b9a6433a91ae6745d3 (patch) | |
tree | e087e3428090111c5c41eeabe924a60d8078f338 /src/mainboard/lenovo/thinkcentre_a58/dsdt.asl | |
parent | f1a3503459317a19d0070d0569c31a41cccf4940 (diff) | |
download | coreboot-a1e46aea79a7d51e006d91b9a6433a91ae6745d3.tar.xz |
mb/lenovo/thinkcentre_a58: Add mainboard
The following was tested:
- Using two DDR2 DIMMs
- S3 sleep and resume (on SeaBIOS it needs sercon disabled)
- Ethernet NIC
- Libgfxinit (native res and textmode)
- SATA
- USB
- 800MHz FSB CPU (Pentium(R) E5200 @ 2.50GHz)
- PS2 Keyboard
- Serial output
TODO:
- Add ACPI code for SuperIO devices (done in a follow-up patch)
- Add documentation
TESTED with SeaBIOS (sercon disabled), Linux 4.19
Change-Id: I483e1143e4095b8a58fed142d31ca7f233a854e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30239
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo/thinkcentre_a58/dsdt.asl')
-rw-r--r-- | src/mainboard/lenovo/thinkcentre_a58/dsdt.asl | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl new file mode 100644 index 0000000000..4eade3dfbb --- /dev/null +++ b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/i82801gx/i82801gx.h> + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20090419 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} |