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authorArthur Heymans <arthur@aheymans.xyz>2019-11-11 20:18:24 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-14 11:30:34 +0000
commit2452afbe04584d48a9d76535f943c0cfc641aa19 (patch)
tree0ce5aed52511660ab274d8a0aeb95cb606a7b57a /src/mainboard/lenovo/thinkcentre_a58
parentaa990e928910e35edb115095898c4668becdf1d8 (diff)
downloadcoreboot-2452afbe04584d48a9d76535f943c0cfc641aa19.tar.xz
mb/*/*(ich7/x4x): Use common early southbridge init
One functional change is that southbridge GPIO init is moved after console init. Change-Id: I53e6f177aadcdaa8c45593e0a8098e8d3c400d27 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36757 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo/thinkcentre_a58')
-rw-r--r--src/mainboard/lenovo/thinkcentre_a58/romstage.c18
1 files changed, 1 insertions, 17 deletions
diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
index d632d9ddbf..8be2c86734 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c
+++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
@@ -17,7 +17,6 @@
#include <console/console.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
-#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h>
#include <northbridge/intel/x4x/x4x.h>
#include <arch/romstage.h>
@@ -27,21 +26,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
-static void mb_lpc_setup(void)
-{
- /* Set the value for GPIO base address register and enable GPIO. */
- pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
- pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
-
- setup_pch_gpios(&mainboard_gpio_map);
-
- /* Enable IOAPIC */
- RCBA8(0x31ff) = 0x03;
- RCBA8(0x31ff);
-
- ich7_setup_cir();
-}
-
void mainboard_romstage_entry(void)
{
// ch0 ch1
@@ -51,13 +35,13 @@ void mainboard_romstage_entry(void)
/* Set southbridge and Super I/O GPIOs. */
i82801gx_lpc_setup();
- mb_lpc_setup();
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
+ i82801gx_early_init();
x4x_early_init();
s3_resume = southbridge_detect_s3_resume();