diff options
author | Alexander Couzens <lynxis@fe80.eu> | 2016-10-12 04:44:19 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2017-05-01 01:08:47 +0200 |
commit | db508565d2483394b709654c57533e55eebace51 (patch) | |
tree | 696aa2f69aaf13cdd78d9f2ec54dc49e7d878ed8 /src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl | |
parent | 7ee81a4a0169242ed40d3e4b1d181cca7bb959be (diff) | |
download | coreboot-db508565d2483394b709654c57533e55eebace51.tar.xz |
mainboard: add support for lenovo x1 carbon gen 1
Based on Thinkpad x230 and schematics.
Verified by autoport.
USB debug port is the left front usb port
Thanks to Holger Levsen for the device.
Change-Id: I97c8e01a3ce0577d7dc9e8df7d33db3b155fe3d6
Tested-on: lenovo x1 carbon gen 1
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16994
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl')
-rw-r--r-- | src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl new file mode 100644 index 0000000000..8ad7ace8e1 --- /dev/null +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} |