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| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-08-31 12:57:08 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-02 18:08:01 +0200 |
| commit | 734b3d1be0773446c8d66205234a817fa10f48db (patch) | |
| tree | fec3072eeec27e18f6b88c9e1215f6d776c3a7f1 /src/mainboard/lenovo/x200/romstage.c | |
| parent | 5cf758d45b70fde40df8d2bf4925eb344b7b9b0b (diff) | |
| download | coreboot-734b3d1be0773446c8d66205234a817fa10f48db.tar.xz | |
lenovo/x200,t400: use gpio.h instead of gpio_setup
Uses gpio.h instead of default_southbridge_gpio_setup to configure
southbridge GPIO's. This is more consistent with how GPIO's are
configured on newer targets.
Change-Id: I6ccd0564b929e958864739b7cde04f5592c58479
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16379
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/lenovo/x200/romstage.c')
| -rw-r--r-- | src/mainboard/lenovo/x200/romstage.c | 21 |
1 files changed, 2 insertions, 19 deletions
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 1deab65639..c1e193a973 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -30,28 +30,11 @@ #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> +#include "gpio.h" #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) -static void default_southbridge_gpio_setup(void) -{ - outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); - outl(0xe1a66dfe, DEFAULT_GPIOBASE + GP_IO_SEL); - outl(0xe3faef3f, DEFAULT_GPIOBASE + GP_LVL); - - /* Disable blink [31:0]. */ - outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); - /* Set input inversion [31:0]. */ - outl(0x00000102, DEFAULT_GPIOBASE + GPI_INV); - - /* Enable GPIOs [60:32]. */ - outl(0x030306f6, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); - /* Set input/output mode [60:32] (0 == out, 1 == in). */ - outl(0x1f55f9f1, DEFAULT_GPIOBASE + GP_IO_SEL2); - /* Set gpio levels [60:32]. */ - outl(0x1dffff53, DEFAULT_GPIOBASE + GP_LVL2); -} static void early_lpc_setup(void) { @@ -93,7 +76,7 @@ void mainboard_romstage_entry(unsigned long bist) gm45_early_reset(); } - default_southbridge_gpio_setup(); + setup_pch_gpios(&x200_gpio_map); /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10); |