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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-04-06 03:41:28 -0500 |
|---|---|---|
| committer | Edward O'Callaghan <edward.ocallaghan@koparo.com> | 2015-05-02 19:13:58 +0200 |
| commit | 289eec8ab755b1dab9ef063dab05dd1c796726fc (patch) | |
| tree | c08ffe5d9135d371d589c9c9b4975624f282b0b6 /src/mainboard/lenovo/x200/romstage.c | |
| parent | b738913ce050cd5a61d902e7024d4881cdb1ae59 (diff) | |
| download | coreboot-289eec8ab755b1dab9ef063dab05dd1c796726fc.tar.xz | |
mainboard/lenovo/x200: Use defines from southbridge for GPIO config
Change-Id: I9f65922d0785e06a173221b3262e73b575087dfd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9321
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/lenovo/x200/romstage.c')
| -rw-r--r-- | src/mainboard/lenovo/x200/romstage.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index f232642871..5f50f325c5 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -40,21 +40,21 @@ static void default_southbridge_gpio_setup(void) { - outl(0x197e23fe, DEFAULT_GPIOBASE + 0x00); - outl(0xe1a66dfe, DEFAULT_GPIOBASE + 0x04); - outl(0xe3faef3f, DEFAULT_GPIOBASE + 0x0c); + outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); + outl(0xe1a66dfe, DEFAULT_GPIOBASE + GP_IO_SEL); + outl(0xe3faef3f, DEFAULT_GPIOBASE + GP_LVL); /* Disable blink [31:0]. */ - outl(0x00000000, DEFAULT_GPIOBASE + 0x18); + outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); /* Set input inversion [31:0]. */ - outl(0x00000102, DEFAULT_GPIOBASE + 0x2c); + outl(0x00000102, DEFAULT_GPIOBASE + GPI_INV); /* Enable GPIOs [60:32]. */ - outl(0x030306f6, DEFAULT_GPIOBASE + 0x30); + outl(0x030306f6, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); /* Set input/output mode [60:32] (0 == out, 1 == in). */ - outl(0x1f55f9f1, DEFAULT_GPIOBASE + 0x34); + outl(0x1f55f9f1, DEFAULT_GPIOBASE + GP_IO_SEL2); /* Set gpio levels [60:32]. */ - outl(0x1dffff53, DEFAULT_GPIOBASE + 0x38); + outl(0x1dffff53, DEFAULT_GPIOBASE + GP_LVL2); } static void early_lpc_setup(void) |