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authorArthur Heymans <arthur@aheymans.xyz>2016-09-30 21:03:23 +0200
committerMartin Roth <martinroth@google.com>2016-10-04 19:03:28 +0200
commit58afca4a1a09f6bb4c28de460791984002408cdc (patch)
treebb22452dd274aa18a0e46a05c57644da3b843705 /src/mainboard/lenovo/x200
parent5e0242b0ec5c44bc684faf4985884ce39d93cdfb (diff)
downloadcoreboot-58afca4a1a09f6bb4c28de460791984002408cdc.tar.xz
nb/gm45: allow use of 352M preallocated ram for igd
The datasheets on gm45: "Mobile IntelĀ® 4 Series Express Chipset Family" mention the possibility of having 352M ram preallocated for the integrated graphic device. This only worked fine if the amount of ram in the system was 3GB or less. When 4G or more is installed, memory is remapped to create a 1GB large pci mmio hole which is not enough and creates conflicts when 352M vram is used. This patch increases the pci mmio hole size on Lenovo x200 to allow 352M vram to work. TEST: build and flash on target with 4GB ram or more, use nvramtool to set gfx_uma_size to 352M and reboot. Change-Id: I5ab066252339ac7d85149d91b09a9eaaaab3b5b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16831 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/lenovo/x200')
-rw-r--r--src/mainboard/lenovo/x200/cmos.layout1
-rw-r--r--src/mainboard/lenovo/x200/devicetree.cb2
2 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout
index 19ead05bee..35d50172fd 100644
--- a/src/mainboard/lenovo/x200/cmos.layout
+++ b/src/mainboard/lenovo/x200/cmos.layout
@@ -136,6 +136,7 @@ enumerations
11 9 96M
11 10 160M
11 11 224M
+11 12 352M
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb
index 200b4bca0f..d9cb783057 100644
--- a/src/mainboard/lenovo/x200/devicetree.cb
+++ b/src/mainboard/lenovo/x200/devicetree.cb
@@ -28,7 +28,7 @@ chip northbridge/intel/gm45
end
end
- register "pci_mmio_size" = "1024"
+ register "pci_mmio_size" = "2048"
device domain 0 on
device pci 00.0 on