nb/intel/gm45: Use a common romstage

This moves a lot of the common romstage boilerplate code to a common
location, while adding a few mainboard specific hooks.

Another difference is that the settings for enable_igd and enable_peg
are now based on the static devicetree settings.

Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

1 files changed, 8 insertions, 87 deletions

diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index c0113562a1..e8bbfb09fd 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -16,27 +16,15 @@
 
 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
 
-#include <stdint.h>
-#include <string.h>
 #include <arch/io.h>
-#include <arch/acpi.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/tsc.h>
-#include <cpu/intel/romstage.h>
-#include <cbmem.h>
-#include <romstage_handoff.h>
-#include <console/console.h>
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/i82801ix/i82801ix.h>
 #include <northbridge/intel/gm45/gm45.h>
 
 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
-#define MCH_DEV PCI_DEV(0, 0, 0)
 
-static void early_lpc_setup(void)
+void mb_setup_lpc(void)
 {
-	/* Set up SuperIO LPC forwards */
-
 	/* Configure serial IRQs.*/
 	pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
 	/* Map COMa on 0x3f8, COMb on 0x2f8. */
@@ -47,82 +35,15 @@ static void early_lpc_setup(void)
 	pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void get_mb_spd_addrmap(u8 *spd_addrmap)
 {
-	sysinfo_t sysinfo;
-	int s3resume = 0;
-	int cbmem_initted;
-	u16 reg16;
-
-	/* basic northbridge setup, including MMCONF BAR */
-	gm45_early_init();
-
-	if (bist == 0)
-		enable_lapic();
-
-	/* First, run everything needed for console output. */
-	i82801ix_early_init();
-	early_lpc_setup();
-	console_init();
-	printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist);
-
-	reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
-	pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
-	if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
-		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
-		gm45_early_reset();
-	}
-
-	setup_pch_gpios(&mainboard_gpio_map);
-
-	/* ASPM related setting, set early by original BIOS. */
-	DMIBAR16(0x204) &= ~(3 << 10);
-
-	/* Check for S3 resume. */
-	const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
-	if (((pm1_cnt >> 10) & 7) == 5) {
-		if (acpi_s3_resume_allowed()) {
-			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-			s3resume = 1;
-			/* Clear SLP_TYPE. This will break stage2 but
-			 * we care for that when we get there.
-			 */
-			outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-		} else {
-			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-		}
-	}
-
-	/* RAM initialization */
-	enter_raminit_or_reset();
-	memset(&sysinfo, 0, sizeof(sysinfo));
-	sysinfo.spd_map[0] = 0x50;
-	sysinfo.spd_map[2] = 0x51;
-	sysinfo.enable_igd = 1;
-	sysinfo.enable_peg = 0;
-	get_gmch_info(&sysinfo);
-	raminit(&sysinfo, s3resume);
-
-	const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
-	/* Disable D4F0 (unknown signal controller). */
-	pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
-
-	init_pm(&sysinfo, 0);
-
-	i82801ix_dmi_setup();
-	gm45_late_init(sysinfo.stepping);
-	i82801ix_dmi_poll_vc1();
-
-	MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
-
-	init_iommu();
+	spd_addrmap[0] = 0x50;
+	spd_addrmap[2] = 0x51;
+}
 
+void mb_post_raminit_setup(void)
+{
 	/* FIXME: make a proper SMBUS mux support.  */
+	/* Set the SMBUS mux to the eeprom */
 	set_gpio(42, GPIO_LEVEL_LOW);
-
-	cbmem_initted = !cbmem_recovery(s3resume);
-
-	romstage_handoff_init(cbmem_initted && s3resume);
-
-	printk(BIOS_SPEW, "exit main()\n");
 }