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| author | Angel Pons <th3fanbus@gmail.com> | 2021-04-02 22:42:53 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-04-05 13:16:22 +0000 |
| commit | e24f97c081f3e134362081913793d5adb90eddd5 (patch) | |
| tree | 0d1836ad9473b51ecca07dc2465a736201b08a8a /src/mainboard/lenovo/x201/devicetree.cb | |
| parent | 83e319d6f5b4802fdc862f4bcbe830ccb9e4dfa6 (diff) | |
| download | coreboot-e24f97c081f3e134362081913793d5adb90eddd5.tar.xz | |
nb/intel/ironlake: Drop `pci_mmio_size`
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.
Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo/x201/devicetree.cb')
| -rw-r--r-- | src/mainboard/lenovo/x201/devicetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6b6543dee3..e142a1c692 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -24,8 +24,6 @@ chip northbridge/intel/ironlake end end - register "pci_mmio_size" = "1024" - device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2193 |