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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-22 22:52:14 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-04-09 12:03:58 +0000
commit2c3fd499cf0672a8da669e40be84112a02b5a77c (patch)
treec2caa870a8923a4a87bfd3507029b0ddf6484114 /src/mainboard/lenovo/x201
parentd538dd1fe70a333c929a2eb7c4106608bcd05257 (diff)
downloadcoreboot-2c3fd499cf0672a8da669e40be84112a02b5a77c.tar.xz
intel/nehalem post-car: Use postcar_frame for MTRR setup
Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: I84f6fa6f37a7348b2d4ad9f08a18bebe4b1e34e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/lenovo/x201')
-rw-r--r--src/mainboard/lenovo/x201/romstage.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 8e8a5df30b..029c5e561c 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -279,12 +279,9 @@ void mainboard_romstage_entry(unsigned long bist)
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
}
-
romstage_handoff_init(s3resume);
- if (s3resume)
- acpi_prepare_for_resume();
- else
+ if (!s3resume)
quick_ram_check();
#if IS_ENABLED(CONFIG_LPC_TPM)