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authorTristan Corrick <tristan@corrick.kiwi>2018-11-30 22:53:50 +1300
committerPatrick Georgi <pgeorgi@google.com>2018-12-03 13:14:06 +0000
commit63626b1a4a31588995ff6f0ba42952b6086cbded (patch)
tree968555763c26df36af3e64b7322b3c68d6c19913 /src/mainboard/lenovo/x201
parent32ceed8f269e48d9d500ee2ec9ba5b3f4435285e (diff)
downloadcoreboot-63626b1a4a31588995ff6f0ba42952b6086cbded.tar.xz
sb/intel/common: Create a common PCH finalise implementation
The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak. Lynx Point now benefits from being able to write-protect the flash chip. For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done in bd82x6x. Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is configured, flashrom reports all flash regions as read-only, and does not manage to alter the contents of the flash chip. Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to work as before. Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/lenovo/x201')
-rw-r--r--src/mainboard/lenovo/x201/smihandler.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c
index fbbec09adc..10ca4d438b 100644
--- a/src/mainboard/lenovo/x201/smihandler.c
+++ b/src/mainboard/lenovo/x201/smihandler.c
@@ -20,6 +20,7 @@
#include <southbridge/intel/ibexpeak/nvs.h>
#include <southbridge/intel/ibexpeak/pch.h>
#include <southbridge/intel/ibexpeak/me.h>
+#include <southbridge/intel/common/finalize.h>
#include <northbridge/intel/nehalem/nehalem.h>
#include <cpu/intel/model_2065x/model_2065x.h>
#include <ec/acpi/ec.h>