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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-17 10:00:28 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-22 10:49:18 +0200
commit8431fcb8c8e248d777723e0a6651b9030d29cf8e (patch)
treec9b06b7c67c8f6fa54d5ae03c59887ada4f0c690 /src/mainboard/lenovo/x201
parentb4f827d45a08d849df9d15abd644e3a98a6f1932 (diff)
downloadcoreboot-8431fcb8c8e248d777723e0a6651b9030d29cf8e.tar.xz
intel/model_2065x: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I616143b55d7c5726dc2475434e3fcb08b8d69bda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15230 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/lenovo/x201')
-rw-r--r--src/mainboard/lenovo/x201/romstage.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 53032f63ae..19b49094fb 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -28,6 +28,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
#include <ec/acpi/ec.h>
#include <delay.h>
#include <timestamp.h>
@@ -174,8 +175,7 @@ static void set_fsb_frequency(void)
smbus_block_write(0x69, 0, 5, block);
}
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_romstage_entry(unsigned long bist)
{
u32 reg32;
int s3resume = 0;