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| author | Jamie Chen <jamie.chen@intel.com> | 2020-04-16 01:42:51 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-13 12:04:32 +0000 |
| commit | 741099239194b01ef153a7b41a9d8389b0b06f8e (patch) | |
| tree | a3856989ebd1b74fa2e66d5590c53f5192e1d82c /src/mainboard/lenovo/x220/cmos.layout | |
| parent | 92ba06fb3e6a5ba089305b6739b1b4344984ba37 (diff) | |
| download | coreboot-741099239194b01ef153a7b41a9d8389b0b06f8e.tar.xz | |
mb/google/puff: add a region to cache SPD data
This patch adds a SPI rom region RW_SPD_CACHE on Puff and it can be used
on spd_cache to reduce reading SPD data from SODIMM by smbus. It's for
saving the boot time and it can be used to trigger MRC retraining when
memory DIMM is changed.
BUG=b:146457985
BRANCH=None
TEST=Build puff successfully and verified below two items.
1. To change memory DIMM can trigger retraining.
2. one DIMM save the boot time : 158ms
two DIMM save the boot time : 265ms
Change-Id: I8d07fddf113a767d62394cb31e33b56f22f74351
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'src/mainboard/lenovo/x220/cmos.layout')
0 files changed, 0 insertions, 0 deletions