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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-18 19:59:23 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-20 21:24:13 +0100
commite258b9a2d52bb31d99405cad4b44047022dc4007 (patch)
treeb9677cb2213830e0e939d1915a5ee7616c7f12e0 /src/mainboard/lenovo/x220
parent38cb82222c9bc5cfae9c679ee4171fae3947b067 (diff)
downloadcoreboot-e258b9a2d52bb31d99405cad4b44047022dc4007.tar.xz
intel sandy/ivy: Improve DIMM replacement detection
When MRC cache is available, first read only the SPD unique identifier bytes required to detect possible DIMM replacement. As this is 11 vs 256 bytes with slow SMBus operations, we save about 70ms for every installed DIMM on normal boot path. In the DIMM replacement case this adds some 10ms per installed DIMM as some SPD gets read twice, but we are on slow RAM training boot path anyways. Change-Id: I294a56e7b7562c3dea322c644b21a15abb033870 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17491 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/lenovo/x220')
-rw-r--r--src/mainboard/lenovo/x220/romstage.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 71ed1a8007..5a1c90af77 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -75,10 +75,10 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 6 },
};
-void mainboard_get_spd(spd_raw_data *spd)
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
- read_spd (&spd[0], 0x50);
- read_spd (&spd[2], 0x51);
+ read_spd (&spd[0], 0x50, id_only);
+ read_spd (&spd[2], 0x51, id_only);
}
void mainboard_early_init(int s3resume)