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authorMarian Tietz <mtcoreboot@gmail.com>2016-01-09 18:18:47 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2016-01-10 18:48:12 +0100
commit7c6c4df68cf6dd7e79851595491f3f45e4ea611f (patch)
tree126f09c81b1e7664c0d47a63a6d61065fdeb3ed2 /src/mainboard/lenovo/x220
parent8846382cbbbf301e313958aadc4bed2522796c1f (diff)
downloadcoreboot-7c6c4df68cf6dd7e79851595491f3f45e4ea611f.tar.xz
lenovo/x220: Enable USB 3 controller
Since only X220 with i7 have the USB3 controller this was probably overlooked. Before this patch lspci on Linux would not show the NEC USB 3 controller as well as the PCI bridge it is behind. After, both the bridge and the NEC controller can be found in the output: 05:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 04) Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331 Signed-off-by: Marian Tietz <mtcoreboot@gmail.com> Reviewed-on: https://review.coreboot.org/12882 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/x220')
-rw-r--r--src/mainboard/lenovo/x220/devicetree.cb4
-rw-r--r--src/mainboard/lenovo/x220/romstage.c2
2 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 9c9ac7c175..9f25658a5e 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -109,7 +109,9 @@ chip northbridge/intel/sandybridge
end
end # PCIe Port #5 (SD)
device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.6 on
+ subsystemid 0x17aa 0x21db
+ end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on
subsystemid 0x17aa 0x21db
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 1d89d92477..ce3f276f89 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -54,7 +54,7 @@ void pch_enable_lpc(void)
void rcba_config(void)
{
/* Disable unused devices (board specific) */
- RCBA32(FD) = 0x1fe41fe3;
+ RCBA32(FD) = 0x1fa41fe3;
RCBA32(BUC) = 0;
}