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authorPatrick Rudolph <siro@das-labor.org>2017-05-04 19:00:33 +0200
committerPatrick Rudolph <siro@das-labor.org>2017-05-21 16:38:34 +0200
commitac27d3688a862074631e3a1390caf85c068d55cb (patch)
tree904158a0566038c8d2c51972e2318370ef5617b2 /src/mainboard/lenovo/x220
parent7565cf1a49bf9688e636e1ebc6a4cb8e1e567e1b (diff)
downloadcoreboot-ac27d3688a862074631e3a1390caf85c068d55cb.tar.xz
mb/*/romstage: Don't lock ETR3 CF9GR in early romstage
Do not lock ETR3 CF9GR in early romstage. As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done in bd82x6x's finalize handler. Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/lenovo/x220')
-rw-r--r--src/mainboard/lenovo/x220/romstage.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 5a1c90af77..15d2c845bb 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -47,8 +47,7 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
- pci_write_config32(PCH_LPC_DEV, 0xac,
- 0x80010000);
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void rcba_config(void)