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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-09-17 02:38:51 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-10-17 11:05:47 +0200 |
| commit | 3dc12c1e19181bb9bacebeda706c39cfb57eb326 (patch) | |
| tree | 5834c1758eea5faa9a61eec7dc8fce62eb05a17c /src/mainboard/lenovo/x220 | |
| parent | cb0d772eef12ce89d31197d0e71b103c7b3cf02c (diff) | |
| download | coreboot-3dc12c1e19181bb9bacebeda706c39cfb57eb326.tar.xz | |
bd82x6x: Consolidate early native USB init
Change-Id: I6189930fd3c69c3497e4cf1a78035e6614761b13
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6923
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/x220')
| -rw-r--r-- | src/mainboard/lenovo/x220/romstage.c | 56 |
1 files changed, 16 insertions, 40 deletions
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 5ea91cf4a9..33d9b5e00e 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -105,45 +105,6 @@ static void rcba_config(void) RCBA32(BUC) = 0; } -static void -init_usb (void) -{ - const u32 rcba_dump[64] = { - /* 3500 */ 0x20000153, 0x20000f57, 0x20000f57, 0x20000f57, - /* 3510 */ 0x20000f57, 0x20000f57, 0x20000153, 0x20000153, - /* 3520 */ 0x20000f57, 0x20000f57, 0x20000f57, 0x20000f57, - /* 3530 */ 0x20000f57, 0x20000f57, 0x00000000, 0x00000000, - /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3560 */ 0x020c0001, 0x000024a3, 0x00040002, 0x01000050, - /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, - /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3590 */ 0x00000003, 0x000000c0, 0x00000000, 0x00000000, - /* 35a0 */ 0x0fc00201, 0x102d0200, 0x00000000, 0x00000000, - /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - }; - int i; - /* Activate PMBAR. */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ - - /* Unlock registers. */ - outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); - - for (i = 0; i < 64; i++) - write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]); - - pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); - - /* Relock registers. */ - outw (0x0000, DEFAULT_PMBASE | 0x003c); -} - #include <cpu/intel/romstage.h> void main(unsigned long bist) { @@ -179,7 +140,22 @@ void main(unsigned long bist) outl(0x00000ff0, DEFAULT_GPIOBASE + 0x44); outl(0x00000fcf, DEFAULT_GPIOBASE + 0x48); - init_usb(); + early_usb_init((struct southbridge_usb_port []) { + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 1, 3 }, + { 1, 1, 3 }, + { 1, 1, -1 }, + { 1, 1, -1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 1, 6 }, + { 1, 1, 5 }, + { 1, 1, 6 }, + { 1, 1, 6 }, + { 1, 1, 7 }, + { 1, 1, 6 }, + }); /* Initialize console device(s) */ console_init(); |