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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-12-29 11:32:27 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-04-28 07:59:13 +0200
commitb85a87b7d6f9f12d5c71c32741c8af731ed6be7e (patch)
tree67553a9c683557ead346dc1c7b155d3eac475090 /src/mainboard/lenovo/x220
parent189f3ba974df8f1b305cfa421a151fe069fc1a6f (diff)
downloadcoreboot-b85a87b7d6f9f12d5c71c32741c8af731ed6be7e.tar.xz
intel SMI handlers: Refactor GPI SMI/SCI routing
Move the GPI interrupt routing selection between SMI/SCI from mainboards to southbridge. There is speculation if this is all just legacy APM stuff that could be removed with a followup. Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7967 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Diffstat (limited to 'src/mainboard/lenovo/x220')
-rw-r--r--src/mainboard/lenovo/x220/smihandler.c34
1 files changed, 4 insertions, 30 deletions
diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c
index 372f280a9f..8208fe735d 100644
--- a/src/mainboard/lenovo/x220/smihandler.c
+++ b/src/mainboard/lenovo/x220/smihandler.c
@@ -119,25 +119,12 @@ static int mainboard_finalized = 0;
int mainboard_smi_apmc(u8 data)
{
- u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
- u8 tmp;
-
- printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
- data);
-
- if (!pmbase)
- return 0;
-
switch (data) {
case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600);
/* route EC_SCI to SCI */
- outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
- tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
- tmp &= ~0x03;
- tmp |= 0x02;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
/* discard all events, and enable attention */
ec_write(0x80, 0x01);
break;
@@ -145,13 +132,8 @@ int mainboard_smi_apmc(u8 data)
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */
ec_set_ports(0x66, 0x62);
- /* route EC_SCI# to SMI */
- outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI),
- pmbase + ALT_GP_SMI_EN);
- tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
- tmp &= ~0x03;
- tmp |= 0x01;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* route EC_SCI to SMI */
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
/* discard all events, and enable attention */
ec_write(0x80, 0x01);
break;
@@ -182,16 +164,8 @@ void mainboard_smi_sleep(u8 slp_typ)
u8 ec_wake = ec_read(0x32);
/* If EC wake events are enabled, enable wake on EC WAKE GPE. */
if (ec_wake & 0x14) {
- u32 gpe_rout;
- u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
-
- /* Enable EC WAKE GPE. */
- outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN);
- gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
/* Redirect EC WAKE GPE to SCI. */
- gpe_rout &= ~(3 << (GPE_EC_WAKE * 2));
- gpe_rout |= (2 << (GPE_EC_WAKE * 2));
- pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
+ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
}
}
}