diff options
author | Bill XIE <persmule@hardenedlinux.org> | 2020-05-08 16:40:48 +0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-29 15:51:23 +0000 |
commit | d87277abbf70b7f29034a503689de47aba7e3052 (patch) | |
tree | 0b6ca4c7d23fbfd63b3781e4e92958765eefb9f6 /src/mainboard/lenovo/x230/variants/x230s/early_init.c | |
parent | c4f5e4e7938de3e8109d33e418ba0596c66809aa (diff) | |
download | coreboot-d87277abbf70b7f29034a503689de47aba7e3052.tar.xz |
mainboard/lenovo/x230: Add ThinkPad x230s as a variant
The code is based on autoport and that for X230. Major differences are:
- Only one DDR3 slot
- HM77 PCH
- M.2 socket instead of mini PCIe
- No docking
- No TPM
Tested:
- CPU i5-3337U
- 8GiB SO-DIMM
- Camera
- PCIe and USB2 on M.2 slot with A key for WLAN
- SATA and USB2 (no SuperSpeed components) on M.2 slot with B key for WWAN
- On board SDHCI connected to PCIe
- USB3 ports
- libgfxinit-based graphics init
- NVRAM options for North and South bridges
- Sound
- ThinkPad EC
- S3
- Linux 4.9 within Debian GNU/Linux stable, loaded from SeaBIOS.
Untested:
- Touch screen, which is said to work under ubuntu but not debian.
Change-Id: Id59cdc5479aaf70809dd1ca613056263661455eb
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41390
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo/x230/variants/x230s/early_init.c')
-rw-r--r-- | src/mainboard/lenovo/x230/variants/x230s/early_init.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x230/variants/x230s/early_init.c b/src/mainboard/lenovo/x230/variants/x230s/early_init.c new file mode 100644 index 0000000000..362e7fa64a --- /dev/null +++ b/src/mainboard/lenovo/x230/variants/x230s/early_init.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + {1, 3, 0}, /* SSP1: Right */ + {1, 3, 1}, /* SSP2: Left, EHCI Debug */ + {0, 1, 3}, /* SSP3 */ + {1, 3, -1}, /* B0P4: WWAN USB */ + {0, 1, 2}, /* B0P5 */ + {0, 1, -1}, /* B0P6 */ + {0, 1, -1}, /* B0P7 */ + {0, 1, -1}, /* B0P8 */ + {0, 1, -1}, /* B1P1 */ + {0, 1, 5}, /* B1P2 */ + {1, 1, -1}, /* B1P3: Fingerprint Reader */ + {0, 1, -1}, /* B1P4 */ + {1, 3, -1}, /* B1P5: WLAN USB */ + {1, 1, -1}, /* B1P6: Camera */ +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); +} |