summaryrefslogtreecommitdiff
path: root/src/mainboard/lenovo/x230
diff options
context:
space:
mode:
authorNicolas Reinecke <nr@das-labor.org>2015-02-01 02:53:35 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-03-10 23:53:17 +0100
commitb0922f0183cb50b9714285c539c387956d86814c (patch)
tree95d390fda6c2e8e0c95afc983c52284e33417b12 /src/mainboard/lenovo/x230
parent60ef456f46d81faa4f15b8a49b39037037b8b643 (diff)
downloadcoreboot-b0922f0183cb50b9714285c539c387956d86814c.tar.xz
lenovo: fix smi gpe + wakeup pin for t420s t520 t530 x220 x230
Set correct gpio routing and enable bits for EC SMI gpio and EC WAKE gpio. Verified with schematics. Change-Id: Ie3b98c4456a870c881e7663b19eb8ca8e5564c5c Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8358 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/x230')
-rw-r--r--src/mainboard/lenovo/x230/devicetree.cb2
-rw-r--r--src/mainboard/lenovo/x230/smihandler.c19
2 files changed, 12 insertions, 9 deletions
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 3a05b5a89a..08c937f286 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2"
- register "gpi8_routing" = "2"
+ register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata)
register "sata_port_map" = "0x7"
diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c
index 6f6cca160c..372f280a9f 100644
--- a/src/mainboard/lenovo/x230/smihandler.c
+++ b/src/mainboard/lenovo/x230/smihandler.c
@@ -33,6 +33,9 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
+#define GPE_EC_SCI 1
+#define GPE_EC_WAKE 13
+
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler
*/
@@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void)
void mainboard_smi_gpi(u32 gpi_sts)
{
- if (gpi_sts & (1 << 12))
+ if (gpi_sts & (1 << GPE_EC_SCI))
mainboard_smi_handle_ec_sci();
}
@@ -129,8 +132,8 @@ int mainboard_smi_apmc(u8 data)
case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600);
- /* route H8SCI to SCI */
- outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ /* route EC_SCI to SCI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
tmp |= 0x02;
@@ -142,8 +145,8 @@ int mainboard_smi_apmc(u8 data)
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */
ec_set_ports(0x66, 0x62);
- /* route H8SCI# to SMI */
- outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
+ /* route EC_SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI),
pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
@@ -183,11 +186,11 @@ void mainboard_smi_sleep(u8 slp_typ)
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* Enable EC WAKE GPE. */
- outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN);
+ outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN);
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
/* Redirect EC WAKE GPE to SCI. */
- gpe_rout &= ~(3 << 26);
- gpe_rout |= (2 << 26);
+ gpe_rout &= ~(3 << (GPE_EC_WAKE * 2));
+ gpe_rout |= (2 << (GPE_EC_WAKE * 2));
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
}
}