diff options
author | Sven Schnelle <svens@stackframe.org> | 2011-02-14 20:02:47 +0000 |
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committer | Peter Stuge <peter@stuge.se> | 2011-02-14 20:02:47 +0000 |
commit | e2ca71efd903a76426b754d4b385fac4a7947390 (patch) | |
tree | c57db9e50323738ac73a4e859c72eb1ff1460800 /src/mainboard/lenovo/x60/acpi/gpe.asl | |
parent | b9122895731212b991e1ef7a2b6acb791db73d91 (diff) | |
download | coreboot-e2ca71efd903a76426b754d4b385fac4a7947390.tar.xz |
Lenovo ThinkPad X60 / X60s Support
Adds support for Lenovo X60 series ThinkPads. So far, only X60s
(Model 1703) has been tested.
It's a basic patch without SMI and ACPI, as this makes it easier to
review. SMI and ACPI patches will follow.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/lenovo/x60/acpi/gpe.asl')
-rw-r--r-- | src/mainboard/lenovo/x60/acpi/gpe.asl | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl b/src/mainboard/lenovo/x60/acpi/gpe.asl new file mode 100644 index 0000000000..34711271a2 --- /dev/null +++ b/src/mainboard/lenovo/x60/acpi/gpe.asl @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (_GPE) +{ + /* The event numbers correspond to the bit numbers in the + * GPE0_EN register PMBASE + 0x2C. + */ + + // Thermal Event + Method (_L00, 0) + { + + } + + // Hot Plug + Method (_L01, 0) + { + + } + + // Software GPE + Method (_L02, 0) + { + + } + + // USB1 + Method (_L03, 0) + { + + } + + // USB2 + Method (_L04, 0) + { + + } + + // AC97 + Method (_L05, 0) + { + + } + + // _L06 TCOSCI + + // SMBus (Reserved!) + Method (_L07, 0) + { + + } + + // COM1/COM2 (RI) + Method (_L08, 0) + { + + } + + // PCIe + Method (_L09, 0) + { + + } + + // _L0A BatLow / Quick Resume + + // PME + Method (_L0B, 0) + { + + } + + // USB3 + Method (_L0C, 0) + { + + } + + // PME B0 + Method (_L0D, 0) + { + + } + + // USB4 + Method (_L0E, 0) + { + + } + + // _L10 - _L1f: GPIn + + // GPI13 + Method (_L1D, 0) + { + + } +} |