lenovo/x60: native vga init: fix code style issues.

Change-Id: I054edffbb38b13559da10180fc2c6cd9929ba162
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3999
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 82 insertions, 82 deletions

diff --git a/src/mainboard/lenovo/x60/i915io.c b/src/mainboard/lenovo/x60/i915io.c
index 9b21094a3b..355286786a 100644
--- a/src/mainboard/lenovo/x60/i915io.c
+++ b/src/mainboard/lenovo/x60/i915io.c
@@ -21,7 +21,7 @@
 #include "i915io.h"
 
 struct iodef iodefs[] = {
-{V,0,},
+{V, 0,},
 {M, 1, "Linux agpgart interface v0.103", 0x0, 0x0, 0},
 {M, 1, "agpgart-intel 0000:00:00.0:Intel 945GM Chipset", 0x0, 0x0, 0},
 {M, 1, "agpgart-intel 0000:00:00.0:detected gtt size:262144K total, 262144K mappable", 0x0, 0x0, 0},
@@ -36,7 +36,7 @@ struct iodef iodefs[] = {
 {R, 1, "", PP_OFF_DELAYS, 0x00000000, 0},
 {W, 1, "", PP_ON_DELAYS, 0x00000000, 0},
 {W, 1, "", PP_OFF_DELAYS, 0x00000000, 0},
-{W, 1, "", INSTPM+0x24,  MI_ARB_C3_LP_WRITE_ENABLE |0x08000800, 0},
+{W, 1, "", INSTPM+0x24,  MI_ARB_C3_LP_WRITE_ENABLE | 0x08000800, 0},
 {W, 1, "", RENDER_RING_BASE, 0x00000000, 0},
 {W, 1, "", RENDER_RING_BASE+0x4, 0x00000000, 0},
 {W, 1, "", RENDER_RING_BASE+0x8, 0x00000000, 0},
@@ -53,13 +53,13 @@ struct iodef iodefs[] = {
 {W, 1, "", FENCE_REG_965_0+0x14, 0x00000000, 0},
 {W, 1, "", FENCE_REG_965_0+0x18, 0x00000000, 0},
 {W, 1, "", FENCE_REG_965_0+0x1c, 0x00000000, 0},
-{R, 1, "", DCC,  DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED | DCC_CHANNEL_XOR_BIT_17 |0x000f0202, 0},
+{R, 1, "", DCC,  DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED | DCC_CHANNEL_XOR_BIT_17 | 0x000f0202, 0},
 {M, 1, "[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).", 0x0, 0x0, 0},
 {M, 1, "[drm] Driver supports precise vblank timestamp query.", 0x0, 0x0, 0},
 {M, 1, "i915 0000:00:02.0:Invalid ROM contents", 0x0, 0x0, 0},
 {M, 1, "[drm] failed to find VBIOS tables", 0x0, 0x0, 0},
 {M, 1, "vgaarb:device changed decodes:PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem", 0x0, 0x0, 0},
-{W, 1, "", VGACNTRL,  VGA_DISP_DISABLE |0x80000000, 0},
+{W, 1, "", VGACNTRL,  VGA_DISP_DISABLE | 0x80000000, 0},
 {R, 1, "", PFIT_CONTROL, 0x00000000, 0},
 {W, 1, "", 0x5100, 0x00000003, 0},
 {W, 1, "", 0x5104, 0x460100a1, 0},
@@ -202,14 +202,14 @@ struct iodef iodefs[] = {
 {W, 1, "", IMR, 0xfffd73ae, 0},
 {W, 1, "", IER, 0x00028053, 0},
 {R, 1, "", PORT_HOTPLUG_EN, 0x00000000, 0},
-{W, 1, "", PORT_HOTPLUG_EN,  CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000220, 0},
-{R, 1, "", PORT_HOTPLUG_EN,  CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000220, 0},
-{W, 1, "", PORT_HOTPLUG_EN,  CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000228, 0},
-{R, 1, "", PORT_HOTPLUG_EN,  CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000228, 0},
-{R, 1, "", PORT_HOTPLUG_EN,  CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000220, 0},
+{W, 1, "", PORT_HOTPLUG_EN,  CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0},
+{R, 1, "", PORT_HOTPLUG_EN,  CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0},
+{W, 1, "", PORT_HOTPLUG_EN,  CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228, 0},
+{R, 1, "", PORT_HOTPLUG_EN,  CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228, 0},
+{R, 1, "", PORT_HOTPLUG_EN,  CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0},
 {R, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0},
-{W, 1, "", PORT_HOTPLUG_STAT,  CRT_HOTPLUG_INT_STATUS |0x00000800, 0},
-{W, 1, "", PORT_HOTPLUG_EN,  CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 |0x00000220, 0},
+{W, 1, "", PORT_HOTPLUG_STAT,  CRT_HOTPLUG_INT_STATUS | 0x00000800, 0},
+{W, 1, "", PORT_HOTPLUG_EN,  CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0},
 {W, 1, "", 0x5100, 0x00000002, 0},
 {W, 1, "", 0x5104, 0x460100a1, 0},
 {R, 2, "", 0x5108, 0x00009c00, 0},
@@ -234,21 +234,21 @@ struct iodef iodefs[] = {
 {W, 1, "", _PIPEACONF, 0x00000000, 0},
 {R, 1, "", _DPLL_A, 0x94020003, 0},
 {R, 1, "", _PIPEACONF, 0x00000000, 0},
-{W, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
-{R, 1, "", _PIPEASTAT,  PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000a03, 0},
-{W, 1, "", _PIPEASTAT,  PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000a03, 0},
+{W, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
+{R, 1, "", _PIPEASTAT,  PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000a03, 0},
+{W, 1, "", _PIPEASTAT,  PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000a03, 0},
 {R, 2, "", _PIPEASTAT, 0x00000000, 0},
-{R, 2, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
-{W, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 2, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
+{W, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
 {R, 1, "", _PIPEASTAT, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
 {W, 1, "", _DSPBCNTR, 0x40000000, 0},
 {R, 1, "", _DSPBCNTR, 0x40000000, 0},
 {W, 1, "", _DSPBCNTR, 0x58000000, 0},
 {W, 1, "", _DSPBSTRIDE, 0x00001400, 0},
 {W, 1, "", _DSPBADDR, 0x00020000, 0},
-{R, 2, "", DSPARB, ( DSPARB_CSTART_SHIFT &0x4)|0x00001d9c, 0},
-{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK |0x80000000, 0},
+{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0},
+{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK | 0x80000000, 0},
 {W, 1, "", FW_BLC, 0x011d011a, 0},
 {W, 1, "", FW_BLC2, 0x00000102, 0},
 {R, 1, "", TV_CTL, 0x00000000, 0},
@@ -273,7 +273,7 @@ struct iodef iodefs[] = {
 {W, 1, "", TV_CSC_V2, 0x06d00200, 0},
 {W, 1, "", TV_CLR_KNOBS, 0x00606000, 0},
 {W, 1, "", TV_CLR_LEVEL, 0x010b00e1, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _DSPBCNTR, 0x58000000, 0},
 {W, 1, "", _DSPBCNTR, 0x58000000, 0},
 {R, 1, "", _DSPBADDR, 0x00020000, 0},
@@ -284,7 +284,7 @@ struct iodef iodefs[] = {
 {W, 1, "", _PFA_CTL_1, 0x80000000, 0},
 {W, 1, "", _PFA_WIN_POS, 0x00360024, 0},
 {W, 1, "", _PFA_WIN_SZ, 0x02640198, 0},
-{W, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{W, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {W, 1, "", _DSPBCNTR, 0x58000000, 0},
 {R, 1, "", _DSPBADDR, 0x00020000, 0},
 {W, 1, "", _DSPBADDR, 0x00020000, 0},
@@ -497,26 +497,26 @@ struct iodef iodefs[] = {
 {R, 1, "", TV_DAC, 0x70000000, 0},
 {W, 1, "", TV_DAC, 0x00000000, 0},
 {W, 1, "", TV_CTL, 0x000c0000, 0},
-{R, 2, "", DSPARB, ( DSPARB_CSTART_SHIFT &0x4)|0x00001d9c, 0},
-{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK |0x80000000, 0},
+{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0},
+{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK | 0x80000000, 0},
 {W, 1, "", INSTPM+0x20, 0x0001002f, 0},
 {W, 1, "", FW_BLC, 0x0101011a, 0},
 {W, 1, "", FW_BLC2, 0x00000102, 0},
-{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK |0x80008000, 0},
+{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK | 0x80008000, 0},
 {R, 1, "", PP_CONTROL, 0xabcd0000, 0},
 {R, 1, "", LVDS, 0x40000000, 0},
 {R, 1, "", _DPLL_A, 0x94020003, 0},
 {W, 3, "", _DPLL_A, 0x94020003, 0},
 {R, 1, "", _DPLL_A, 0x94020003, 0},
-{R, 2, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 2, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _DSPBCNTR, 0x58000000, 0},
 {W, 1, "", _DSPBCNTR, 0xd8000000, 0},
 {R, 1, "", _DSPBADDR, 0x00020000, 0},
 {W, 1, "", _DSPBADDR, 0x00020000, 0},
-{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
-{W, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
+{W, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
 {R, 2, "", _PIPEASTAT, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
 {W, 1, "", _PALETTE_A, 0x00000000, 0},
 {W, 1, "", _PALETTE_A+0x4, 0x00010101, 0},
 {W, 1, "", _PALETTE_A+0x8, 0x00020202, 0},
@@ -781,96 +781,96 @@ struct iodef iodefs[] = {
 {R, 1, "", LVDS, 0x40000000, 0},
 {R, 1, "", _FDI_TXB_CTL, 0x00000000, 0},
 {R, 1, "", TV_CTL, 0x800c0000, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _PIPEBCONF, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
-{W, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
+{W, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
 {R, 2, "", _PIPEASTAT, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
 {R, 1, "", TV_DAC, 0x70000000, 0},
 {R, 1, "", TV_CTL, 0x800c0000, 0},
 {W, 1, "", TV_CTL, 0x000c0007, 0},
 {W, 1, "", TV_DAC, 0x0f0000aa, 0},
-{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
-{W, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
+{W, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
 {R, 2, "", _PIPEASTAT, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
 {R, 1, "", TV_DAC, 0x7f0000aa, 0},
 {W, 1, "", TV_DAC, 0x70000000, 0},
 {W, 1, "", TV_CTL, 0x800c0000, 0},
-{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
-{W, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
+{W, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
 {R, 4, "", _PIPEASTAT, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
 {R, 1, "", TV_CTL, 0x800c0000, 0},
 {W, 1, "", TV_CTL, 0x000c0000, 0},
 {W, 1, "", INSTPM, 0x08000800, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x62029b1b, 0},
 {R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6217572c, 0},
 {R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
 {R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x63156af7, 0},
 {R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
 {R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x64137fac, 0},
 {R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
 {R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6510b8c6, 0},
 {R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6607c3b5, 0},
 {R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x661c804f, 0},
 {R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
 {R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x671a949c, 0},
 {R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
 {R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6818a96d, 0},
 {R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
 {R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6915e1d1, 0},
 {R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6a0cec77, 0},
 {R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6b04d273, 0},
 {R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
 {R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6c02e710, 0},
 {R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
 {R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _VTOTAL_A, 0x044f03ff, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6d00fb0c, 0},
 {R, 1, "", _HTOTAL_A, 0x06af04ff, 0},
 {R, 1, "", _VBLANK_A, 0x044f03ff, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
 {R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6d1b0b04, 0},
 {R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0},
@@ -878,20 +878,20 @@ struct iodef iodefs[] = {
 {W, 1, "", _DSPBCNTR, 0x58000000, 0},
 {R, 1, "", _DSPBADDR, 0x00020000, 0},
 {W, 1, "", _DSPBADDR, 0x00020000, 0},
-{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
-{W, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
+{W, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
 {R, 2, "", _PIPEASTAT, 0x00000000, 0},
-{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS |0x00000203, 0},
+{R, 1, "", _PIPEASTAT,  PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0},
 {R, 1, "", _DSPACNTR, 0x00000000, 0},
 {R, 1, "", _DSPBCNTR, 0x58000000, 0},
-{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE |0x80000000, 0},
+{R, 1, "", _PIPEACONF,  PIPECONF_ENABLE | 0x80000000, 0},
 {W, 1, "", _PIPEACONF, 0x00000000, 0},
 {R, 2, "", _PIPEADSL, 0x000003ff, 0},
 {R, 1, "", _PIPEACONF, 0x00000000, 0},
 {R, 1, "", _DPLL_A, 0x94020003, 0},
 {W, 1, "", _DPLL_A, 0x14020003, 0},
-{R, 2, "", DSPARB, ( DSPARB_CSTART_SHIFT &0x4)|0x00001d9c, 0},
-{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK |0x80000000, 0},
+{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0},
+{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK | 0x80000000, 0},
 {W, 1, "", FW_BLC, 0x011d011a, 0},
 {W, 1, "", FW_BLC2, 0x00000102, 0},
 {R, 1, "", _DSPBCNTR, 0x58000000, 0},
@@ -908,11 +908,11 @@ struct iodef iodefs[] = {
 {R, 1, "", _PIPEBCONF, 0x00000000, 0},
 {R, 2, "", LVDS, 0x40000000, 0},
 {W, 1, "", _FPB0, 0x00020e09, 0},
-{W, 1, "", _FPB1,  FP_M1_DIV_SHIFT | DPLLA_INPUT_BUFFER_ENABLE | VF_UNIT_CLOCK_GATE_DISABLE |0x00020e09, 0},
-{W, 1, "", _DPLL_B,  DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS |0x18046000, 0},
+{W, 1, "", _FPB1,  FP_M1_DIV_SHIFT | DPLLA_INPUT_BUFFER_ENABLE | VF_UNIT_CLOCK_GATE_DISABLE | 0x00020e09, 0},
+{W, 1, "", _DPLL_B,  DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x18046000, 0},
 {R, 1, "", LVDS, 0x40000000, 0},
-{W, 1, "", LVDS,  LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 |0xc0300300, 0},
-{W, 2, "", _DPLL_B,  DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS |0x98046000, 0},
+{W, 1, "", LVDS,  LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0},
+{W, 2, "", _DPLL_B,  DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0},
 {R, 1, "", _PIPEBCONF, 0x00000000, 0},
 {W, 1, "", _HTOTAL_B, 0x053f03ff, 0},
 {W, 1, "", _HBLANK_B, 0x053f03ff, 0},
@@ -924,7 +924,7 @@ struct iodef iodefs[] = {
 {W, 1, "", _DSPASIZE, 0x02ff03ff, 0},
 {W, 1, "", _DSPASTRIDE+0x4, 0x00000000, 0},
 {W, 1, "", _PIPEBCONF, 0x00000000, 0},
-{R, 1, "", _DPLL_B,  DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS |0x98046000, 0},
+{R, 1, "", _DPLL_B,  DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0},
 {R, 1, "", _PIPEBCONF, 0x00000000, 0},
 {W, 1, "", _PIPEBCONF, 0x80000000, 0},
 {R, 1, "", _PIPEBSTAT, 0x00000040, 0},
@@ -939,21 +939,21 @@ struct iodef iodefs[] = {
 {W, 1, "", _DSPACNTR, 0x59000000, 0},
 {W, 1, "", _DSPASTRIDE, 0x00001000, 0},
 {W, 1, "", _DSPAADDR, 0x00020000, 0},
-{R, 2, "", DSPARB, ( DSPARB_CSTART_SHIFT &0x4)|0x00001d9c, 0},
-{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK |0x80000000, 0},
+{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0},
+{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK | 0x80000000, 0},
 {W, 1, "", FW_BLC, 0x011d011a, 0},
 {W, 1, "", FW_BLC2, 0x00000102, 0},
-{R, 2, "", DSPARB, ( DSPARB_CSTART_SHIFT &0x4)|0x00001d9c, 0},
-{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK |0x80000000, 0},
+{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0},
+{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK | 0x80000000, 0},
 {W, 1, "", INSTPM+0x20, 0x0001003f, 0},
 {W, 1, "", FW_BLC, 0x011d0109, 0},
 {W, 1, "", FW_BLC2, 0x00000102, 0},
-{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK |0x80008000, 0},
+{W, 1, "", INSTPM+0x20,  FW_BLC_SELF_EN_MASK | 0x80008000, 0},
 {R, 1, "", PP_CONTROL, 0xabcd0000, 0},
-{R, 1, "", LVDS,  LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 |0xc0300300, 0},
-{R, 1, "", _DPLL_B,  DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS |0x98046000, 0},
-{W, 3, "", _DPLL_B,  DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS |0x98046000, 0},
-{R, 1, "", _DPLL_B,  DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS |0x98046000, 0},
+{R, 1, "", LVDS,  LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0},
+{R, 1, "", _DPLL_B,  DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0},
+{W, 3, "", _DPLL_B,  DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0},
+{R, 1, "", _DPLL_B,  DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0},
 {R, 2, "", _PIPEBCONF, 0x80000000, 0},
 {R, 1, "", _DSPACNTR,  0x59000000, 0},
 {W, 1, "", _DSPACNTR,  0xd9000000, 0},
@@ -1219,22 +1219,22 @@ struct iodef iodefs[] = {
 {W, 1, "", 0xabf4, 0x00fdfdfd, 0},
 {W, 1, "", 0xabf8, 0x00fefefe, 0},
 {W, 1, "", 0xabfc, 0x00ffffff, 0},
-{R, 1, "", LVDS,  LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 |0xc0300300, 0},
-{W, 1, "", LVDS,  LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 |0xc0300300, 0},
+{R, 1, "", LVDS,  LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0},
+{W, 1, "", LVDS,  LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0},
 {W, 1, "", PFIT_PGM_RATIOS, 0x00000000, 0},
-{W, 1, "", PFIT_CONTROL, ( PFIT_PIPE_SHIFT &0x8)|0x00000008, 0},
+{W, 1, "", PFIT_CONTROL, (PFIT_PIPE_SHIFT & 0x8) | 0x00000008, 0},
 {R, 1, "", PP_CONTROL, 0xabcd0000, 0},
-{W, 1, "", PP_CONTROL,  POWER_TARGET_ON |0xabcd0001, 0},
-{R, 1, "", PP_STATUS,  PP_READY |( PP_SEQUENCE_SHIFT &0x8)|0x4000000a, 0},
-{R, 1, "", PP_STATUS,  PP_ON | PP_READY | PP_SEQUENCE_POWER_UP |( PP_SEQUENCE_SHIFT &0x8)|0xd000000a, 0},
+{W, 1, "", PP_CONTROL,  POWER_TARGET_ON | 0xabcd0001, 0},
+{R, 1, "", PP_STATUS,  PP_READY | (PP_SEQUENCE_SHIFT & 0x8) | 0x4000000a, 0},
+{R, 1, "", PP_STATUS,  PP_ON | PP_READY | PP_SEQUENCE_POWER_UP | (PP_SEQUENCE_SHIFT & 0x8) | 0xd000000a, 0},
 {R, 1, "", BLC_PWM_CTL, 0x00000000, 0},
 {M, 1, "i915:fixme:max PWM is zero", 0x0, 0x0, 0},
 {R, 1, "", BLC_PWM_CTL, 0x00000000, 0},
 {W, 1, "", BLC_PWM_CTL, 0x00000002, 0},
-{R, 2, "", LVDS,  LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 |0xc0300300, 0},
+{R, 2, "", LVDS,  LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0},
 {R, 1, "", _FDI_TXB_CTL, 0x00000000, 0},
 {R, 1, "", TV_CTL, 0x000c0000, 0},
-{R, 1, "", LVDS,  LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 |0xc0300300, 0},
+{R, 1, "", LVDS,  LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0},
 {R, 1, "", _FDI_TXB_CTL, 0x00000000, 0},
 {R, 1, "", TV_CTL, 0x000c0000, 0},
 {R, 1, "", _PIPEACONF, 0x00000000, 0},
@@ -2270,4 +2270,4 @@ struct iodef iodefs[] = {
 {0,},
 };
 
-int niodefs = sizeof (iodefs) / sizeof (iodefs[0]);
+int niodefs = sizeof(iodefs) / sizeof(iodefs[0]);