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authorArthur Heymans <arthur@aheymans.xyz>2019-01-04 14:23:54 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-09 09:56:06 +0000
commit4513020064cc4765e723f6f3cc2b8a45a0dc6545 (patch)
treee9b31b8b64518a62f6a7885a1de54171471c918b /src/mainboard/lenovo/x60
parent907bd5d44e574227baa1f5b3c00b31b8dc351096 (diff)
downloadcoreboot-4513020064cc4765e723f6f3cc2b8a45a0dc6545.tar.xz
cpu/intel: Use the common code to initialize the romstage timestamps
The initial timestamps are now pushed on the stack when entering the romstage C code. Tested on Asus P5QC. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/x60')
-rw-r--r--src/mainboard/lenovo/x60/romstage.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 9c5930ebb1..7b75d16444 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -24,7 +24,6 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
-#include <timestamp.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
@@ -166,10 +165,6 @@ void mainboard_romstage_entry(unsigned long bist)
int s3resume = 0;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
-
- timestamp_init(get_initial_timestamp());
- timestamp_add_now(TS_START_ROMSTAGE);
-
if (bist == 0)
enable_lapic();