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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 10:00:28 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-21 00:49:12 +0200 |
| commit | 15fa992cc8467b4cbd8ebea62e3e4c947827137e (patch) | |
| tree | 99e598cc9f4d088a57e04218f2f979a83a6158d6 /src/mainboard/lenovo | |
| parent | 4c3de9c3edd7cb6fabc72337171862930354f0bf (diff) | |
| download | coreboot-15fa992cc8467b4cbd8ebea62e3e4c947827137e.tar.xz | |
intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15229
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/lenovo')
| -rw-r--r-- | src/mainboard/lenovo/t400/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t60/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x200/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/romstage.c | 4 |
4 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 16676faa02..dbec8d0e90 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -23,13 +23,13 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> +#include <cpu/intel/romstage.h> #include <cbmem.h> #include <lib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> -#include <cpu/intel/romstage.h> #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) @@ -67,7 +67,7 @@ static void early_lpc_setup(void) pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681); } -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { sysinfo_t sysinfo; int s3resume = 0; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index ef86e51142..3ed6afde6d 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -30,6 +30,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> #include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -199,8 +200,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; int dock_err; diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 91500f4774..7d4bc61f9a 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -23,13 +23,13 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> +#include <cpu/intel/romstage.h> #include <cbmem.h> #include <lib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> -#include <cpu/intel/romstage.h> #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) @@ -67,7 +67,7 @@ static void early_lpc_setup(void) pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681); } -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { sysinfo_t sysinfo; int s3resume = 0; diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index a60e05678d..1f249a624a 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -30,6 +30,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> #include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> @@ -206,8 +207,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; |