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authorAngel Pons <th3fanbus@gmail.com>2020-05-21 15:14:07 +0200
committerNico Huber <nico.h@gmx.de>2020-05-26 11:46:21 +0000
commit7e577ad22f2f7fb6e2fca062f87c93e1c1dc3344 (patch)
tree6c0f03073cc094db0a0f5da292e9bb080e0a878e /src/mainboard/lenovo
parent5f82370d7bc4ba385ae8911cbfdabd4450f0e944 (diff)
downloadcoreboot-7e577ad22f2f7fb6e2fca062f87c93e1c1dc3344.tar.xz
AGESA f14/f15tn/f16kb: Factor out memory settings
We use the same values everywhere, so we might as well factor them out. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ie6f166034d5d642dff37730a8d83264fb2e019b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src/mainboard/lenovo')
-rw-r--r--src/mainboard/lenovo/g505s/buildOpts.c11
1 files changed, 0 insertions, 11 deletions
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
index f4993d6450..fd1c977da4 100644
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -346,16 +346,5 @@ SCI_MAP_CONTROL lenovo_g505s_sci_map[] = {
};
#define BLDCFG_FCH_SCI_MAP_LIST (&lenovo_g505s_sci_map[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
/* AGESA nonsense: this header depends on the definitions above */
#include <PlatformInstall.h>