summaryrefslogtreecommitdiff
path: root/src/mainboard/lenovo
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2018-10-27 09:41:02 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-11-12 09:22:18 +0000
commitd2b9ec13622d34714b4ecf8b9daf53b32665d3d7 (patch)
tree205a6f66c9ece4b05010b0c33a8c174bc954249c /src/mainboard/lenovo
parenta9a1913d4d3f27f681b6ef980f064b57da8c1a68 (diff)
downloadcoreboot-d2b9ec13622d34714b4ecf8b9daf53b32665d3d7.tar.xz
src: Remove unneeded include "{arch,cpu}/cpu.h"
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/lenovo')
-rw-r--r--src/mainboard/lenovo/g505s/mptable.c2
-rw-r--r--src/mainboard/lenovo/t520/romstage.c2
-rw-r--r--src/mainboard/lenovo/x1_carbon_gen1/romstage.c1
-rw-r--r--src/mainboard/lenovo/x220/romstage.c1
-rw-r--r--src/mainboard/lenovo/x230/romstage.c2
5 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c
index e94243f446..66f8f463f1 100644
--- a/src/mainboard/lenovo/g505s/mptable.c
+++ b/src/mainboard/lenovo/g505s/mptable.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
@@ -23,7 +22,6 @@
#include <string.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
-
u8 picr_data[0x54] = {
0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index c9a7f8e9ac..0ad74f56e1 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -29,8 +29,6 @@
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
-#include <cbfs.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
index bd1c6a3180..90bf2ebe26 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
@@ -31,7 +31,6 @@
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
#include <cbfs.h>
void pch_enable_lpc(void)
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 7ca05843ce..36fd3ca8db 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -30,7 +30,6 @@
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
#include <cpu/x86/msr.h>
void pch_enable_lpc(void)
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index d0ff67e888..4c946411f3 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -29,8 +29,6 @@
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
-#include <cbfs.h>
void pch_enable_lpc(void)
{