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authorArthur Heymans <arthur@aheymans.xyz>2017-04-05 12:05:12 +0200
committerPatrick Rudolph <siro@das-labor.org>2018-10-27 13:22:06 +0000
commit40b0fc3f8b81d9c38e5c0fda494ba645c3b426e8 (patch)
treeb674bfe40819fb4928d0bdb15f5a582f659f2ccb /src/mainboard/lenovo
parent5a5f6a76ec8806043020c83d016c0fea3c04f70b (diff)
downloadcoreboot-40b0fc3f8b81d9c38e5c0fda494ba645c3b426e8.tar.xz
mb/lenovo/x200: Link gpio map instead of including a header
Linking should allow to link depending on possible future variants. E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c etc. This commit follows up on commit 7dee9745 with Change-Id I88b5ef8e12ac606751952a493f626e1b146e98f7 ("mb/lenovo/x201: Link gpio map instead of including a header"). Change-Id: Ibdb96deafbe422bf50fd2e1fc56a57ae53ccd5a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo')
-rw-r--r--src/mainboard/lenovo/x200/Makefile.inc1
-rw-r--r--src/mainboard/lenovo/x200/gpio.c (renamed from src/mainboard/lenovo/x200/gpio.h)7
-rw-r--r--src/mainboard/lenovo/x200/romstage.c4
3 files changed, 4 insertions, 8 deletions
diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc
index 69e8c4ef6a..c10bc70e67 100644
--- a/src/mainboard/lenovo/x200/Makefile.inc
+++ b/src/mainboard/lenovo/x200/Makefile.inc
@@ -16,5 +16,6 @@
ramstage-y += dock.c
ramstage-y += cstates.c
ramstage-y += blc.c
+romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/x200/gpio.h b/src/mainboard/lenovo/x200/gpio.c
index 2c14719f98..5906fc311f 100644
--- a/src/mainboard/lenovo/x200/gpio.h
+++ b/src/mainboard/lenovo/x200/gpio.c
@@ -11,9 +11,6 @@
* GNU General Public License for more details.
*/
-#ifndef LENOVO_X200_GPIO_H
-#define LENOVO_X200_GPIO_H
-
#include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
@@ -296,7 +293,7 @@ const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio63 = GPIO_LEVEL_LOW,
};
-const struct pch_gpio_map x200_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
@@ -310,5 +307,3 @@ const struct pch_gpio_map x200_gpio_map = {
.level = &pch_gpio_set2_level,
},
};
-
-#endif
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index 8c3e2b2c3f..6a230c9455 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -27,9 +27,9 @@
#include <lib.h>
#include <romstage_handoff.h>
#include <console/console.h>
+#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
-#include "gpio.h"
#include <timestamp.h>
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
@@ -79,7 +79,7 @@ void mainboard_romstage_entry(unsigned long bist)
gm45_early_reset();
}
- setup_pch_gpios(&x200_gpio_map);
+ setup_pch_gpios(&mainboard_gpio_map);
/* ASPM related setting, set early by original BIOS. */
DMIBAR16(0x204) &= ~(3 << 10);