i945: consolidate sb & nb early inits

Change-Id: I00c2c725de5b982a5e4f584b77b09017a5bc0a72
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7062
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)

2 files changed, 9 insertions, 91 deletions

diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index f11b33e9ca..f0ebcbc2a7 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -209,9 +209,8 @@ static void early_ich7_init(void)
 #include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
-	u32 reg32;
-	int boot_mode = 0, dock_err;
-	int cbmem_was_initted;
+	int s3resume = 0;
+	int dock_err;
 	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };
 
 
@@ -262,21 +261,7 @@ void main(unsigned long bist)
 	 */
 	i945_early_initialization();
 
-	/* Read PM1_CNT */
-	reg32 = inl(DEFAULT_PMBASE + 0x04);
-	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
-	if (((reg32 >> 10) & 7) == 5) {
-		if (acpi_s3_resume_allowed()) {
-			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-			boot_mode = 2;
-			/* Clear SLP_TYPE. This will break stage2 but
-			 * we care for that when we get there.
-			 */
-			outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-		} else {
-			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-		}
-	}
+	s3resume = southbridge_detect_s3_resume();
 
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
@@ -286,7 +271,7 @@ void main(unsigned long bist)
 #endif
 
 	timestamp_add_now(TS_BEFORE_INITRAM);
-	sdram_initialize(boot_mode, spd_addrmap);
+	sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
 	timestamp_add_now(TS_AFTER_INITRAM);
 
 	/* Perform some initialization that must run before stage2 */
@@ -301,32 +286,7 @@ void main(unsigned long bist)
 	fixup_i945_errata();
 
 	/* Initialize the internal PCIe links before we go into stage2 */
-	i945_late_initialization();
-
-	MCHBAR16(SSKPD) = 0xCAFE;
-
-	cbmem_was_initted = !cbmem_recovery(boot_mode==2);
-
-#if CONFIG_HAVE_ACPI_RESUME
-	/* If there is no high memory area, we didn't boot before, so
-	 * this is not a resume. In that case we just create the cbmem toc.
-	 */
-	if ((boot_mode == 2) && cbmem_was_initted) {
-		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-
-		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
-		 * through stage 2. We could keep stuff like stack and heap in high tables
-		 * memory completely, but that's a wonderful clean up task for another
-		 * day.
-		 */
-		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
-
-		/* Magic for S3 resume */
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
-	}
-#endif
+	i945_late_initialization(s3resume);
 
 	timestamp_add_now(TS_END_ROMSTAGE);
-
 }
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 943143a506..1310b3377e 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -216,9 +216,7 @@ static void early_ich7_init(void)
 #include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
-	u32 reg32;
-	int boot_mode = 0;
-	int cbmem_was_initted;
+	int s3resume = 0;
 	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };
 
 
@@ -264,21 +262,7 @@ void main(unsigned long bist)
 	 */
 	i945_early_initialization();
 
-	/* Read PM1_CNT */
-	reg32 = inl(DEFAULT_PMBASE + 0x04);
-	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
-	if (((reg32 >> 10) & 7) == 5) {
-		if (acpi_s3_resume_allowed()) {
-			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-			boot_mode = 2;
-			/* Clear SLP_TYPE. This will break stage2 but
-			 * we care for that when we get there.
-			 */
-			outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-		} else {
-			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-		}
-	}
+	s3resume = southbridge_detect_s3_resume();
 
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
@@ -288,7 +272,7 @@ void main(unsigned long bist)
 #endif
 
 	timestamp_add_now(TS_BEFORE_INITRAM);
-	sdram_initialize(boot_mode, spd_addrmap);
+	sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
 	timestamp_add_now(TS_AFTER_INITRAM);
 
 	/* Perform some initialization that must run before stage2 */
@@ -303,33 +287,7 @@ void main(unsigned long bist)
 	fixup_i945_errata();
 
 	/* Initialize the internal PCIe links before we go into stage2 */
-	i945_late_initialization();
-
-	MCHBAR16(SSKPD) = 0xCAFE;
-
-	cbmem_was_initted = !cbmem_recovery(boot_mode==2);
-
-#if CONFIG_HAVE_ACPI_RESUME
-	/* If there is no high memory area, we didn't boot before, so
-	 * this is not a resume. In that case we just create the cbmem toc.
-	 */
-	if ((boot_mode == 2) && cbmem_was_initted) {
-		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-
-		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
-		 * through stage 2. We could keep stuff like stack and heap in high tables
-		 * memory completely, but that's a wonderful clean up task for another
-		 * day.
-		 */
-		if (resume_backup_memory)
-			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE,
-			       HIGH_MEMORY_SAVE);
-
-		/* Magic for S3 resume */
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
-				   SKPAD_ACPI_S3_MAGIC);
-	}
-#endif
+	i945_late_initialization(s3resume);
 
 	timestamp_add_now(TS_END_ROMSTAGE);