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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-28 13:40:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 09:04:26 +0000 |
| commit | 58b9eeca32090e286e3eefeb9a8711a5274d8ad7 (patch) | |
| tree | 36ac23580ebc2514a3472bceb307a48fc58a5bd0 /src/mainboard/lenovo | |
| parent | ca3405ff3272234d8f062dc36c8dd27ab8c63bc6 (diff) | |
| download | coreboot-58b9eeca32090e286e3eefeb9a8711a5274d8ad7.tar.xz | |
mb/lenovo: Get rid of whitespace before tab
Change-Id: I958fe66655cc3c589ce6709b83c56a9472628324
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/lenovo')
| -rw-r--r-- | src/mainboard/lenovo/g505s/acpi/gpe.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/g505s/acpi/sleep.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/g505s/buildOpts.c | 10 | ||||
| -rw-r--r-- | src/mainboard/lenovo/g505s/mainboard.h | 2 |
4 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/lenovo/g505s/acpi/gpe.asl b/src/mainboard/lenovo/g505s/acpi/gpe.asl index deecdc63f2..ace1d2692e 100644 --- a/src/mainboard/lenovo/g505s/acpi/gpe.asl +++ b/src/mainboard/lenovo/g505s/acpi/gpe.asl @@ -73,4 +73,4 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/lenovo/g505s/acpi/sleep.asl b/src/mainboard/lenovo/g505s/acpi/sleep.asl index 947a2f2d43..d516ccedb0 100644 --- a/src/mainboard/lenovo/g505s/acpi/sleep.asl +++ b/src/mainboard/lenovo/g505s/acpi/sleep.asl @@ -44,7 +44,7 @@ Method(\_PTS, 1) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 3e28a301df..9ef46d5708 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -169,11 +169,11 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 #if IS_ENABLED(CONFIG_GFXUMA) -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif #define BLDCFG_IOMMU_SUPPORT TRUE diff --git a/src/mainboard/lenovo/g505s/mainboard.h b/src/mainboard/lenovo/g505s/mainboard.h index 7beb342da9..0a7ccd72dc 100644 --- a/src/mainboard/lenovo/g505s/mainboard.h +++ b/src/mainboard/lenovo/g505s/mainboard.h @@ -30,7 +30,7 @@ /* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but * we make the distinction between GEVENT pin and SCI. */ -#define EC_SCI_GPE EC_SCI_GEVENT +#define EC_SCI_GPE EC_SCI_GEVENT #define EC_LID_GPE EC_LID_GEVENT #define PME_GPE 0x0b #define PCIE_GPE 0x18 |