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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-20 06:43:46 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-28 07:06:24 +0200 |
commit | 0637e567e13adab5b204a33fc57a54f437761f3f (patch) | |
tree | c25c9e838789ed927abb7b487b1050596032ab9d /src/mainboard/lenovo | |
parent | fd22b0847379fac6ef847aeef0de183fd50a9ca2 (diff) | |
download | coreboot-0637e567e13adab5b204a33fc57a54f437761f3f.tar.xz |
lenovo/g505s: Switch away from AGESA_LEGACY
Change-Id: I857486cb80bc01e695ac9592a0a0dc577dfc0d12
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18715
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/lenovo')
-rw-r--r-- | src/mainboard/lenovo/g505s/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/lenovo/g505s/romstage.c | 71 |
2 files changed, 2 insertions, 70 deletions
diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 8006beaae3..aac3a8417d 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -18,7 +18,6 @@ if BOARD_LENOVO_G505S config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP - select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY15_RL select NORTHBRIDGE_AMD_AGESA_FAMILY15_RL select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index 94f62611ef..c05b87a0ec 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -13,77 +13,10 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesa_helper.h> - -#include <arch/acpi.h> -#include <arch/cpu.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <cbmem.h> -#include <console/console.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/car.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <stdint.h> -#include <string.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/agesa/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ } |