diff options
| author | Martin Roth <martinroth@google.com> | 2017-06-24 21:53:37 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-06 00:19:56 +0000 |
| commit | 356b519049e6d40e15b2e4a85cae654e2e8df8ba (patch) | |
| tree | 734c42399af1d7ee2f25588e2bd962922e514f0a /src/mainboard/lenovo | |
| parent | f95911ad3765c0f94db241b0c95a6c0a8c608077 (diff) | |
| download | coreboot-356b519049e6d40e15b2e4a85cae654e2e8df8ba.tar.xz | |
mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol references
Change-Id: I1f906c8c465108017bc4d08534653233078ef32d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/lenovo')
| -rw-r--r-- | src/mainboard/lenovo/g505s/buildOpts.c | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t400/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x200/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x201/romstage.c | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index eda1a4d27a..80b91ba4a8 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -169,7 +169,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 1a5c17caaf..2d35650b0a 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -94,7 +94,7 @@ void mainboard_romstage_entry(unsigned long bist) /* Check for S3 resume. */ const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); if (((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Resume from S3 detected.\n"); s3resume = 1; /* Clear SLP_TYPE. This will break stage2 but diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 02f7116f6e..e3f4686250 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -89,7 +89,7 @@ void mainboard_romstage_entry(unsigned long bist) /* Check for S3 resume. */ const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); if (((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Resume from S3 detected.\n"); s3resume = 1; /* Clear SLP_TYPE. This will break stage2 but diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 7634de8e98..e8312d75cf 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -286,7 +286,7 @@ void mainboard_romstage_entry(unsigned long bist) else quick_ram_check(); -#if CONFIG_LPC_TPM +#if IS_ENABLED(CONFIG_LPC_TPM) init_tpm(s3resume); #endif } |