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authorArthur Heymans <arthur@aheymans.xyz>2016-11-29 14:13:43 +0100
committerMartin Roth <martinroth@google.com>2017-01-06 18:14:00 +0100
commit62902ca45de871aa59657dd8ec1858c301595634 (patch)
tree43b21ab2ec87ec5b41f875efb69be8bb494b0fa7 /src/mainboard/lenovo
parent40843efe5d6dddff19a0d7c8c5fe84c75448e739 (diff)
downloadcoreboot-62902ca45de871aa59657dd8ec1858c301595634.tar.xz
sb/ich7: Use common/gpio.h to set up GPIOs
This is more consistent with newer Intel targets. This a static struct so it is initialized to 0 by default. To make it more readable: * only setting to GPIO mode is made explicit; * only pins in GPIO mode are either set to input or output since this is ignored in native mode; * only output pins are set high or low, since this is read-only on input; * blink is only operational on output pins, non-blink is not set explicitly; * invert is only operational on input pins, non-invert is not set explicitly. Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17639 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/lenovo')
-rw-r--r--src/mainboard/lenovo/t60/Makefile.inc1
-rw-r--r--src/mainboard/lenovo/t60/gpio.c112
-rw-r--r--src/mainboard/lenovo/t60/romstage.c36
-rw-r--r--src/mainboard/lenovo/x60/Makefile.inc1
-rw-r--r--src/mainboard/lenovo/x60/gpio.c111
-rw-r--r--src/mainboard/lenovo/x60/romstage.c43
6 files changed, 229 insertions, 75 deletions
diff --git a/src/mainboard/lenovo/t60/Makefile.inc b/src/mainboard/lenovo/t60/Makefile.inc
index 065c42319a..8473a13505 100644
--- a/src/mainboard/lenovo/t60/Makefile.inc
+++ b/src/mainboard/lenovo/t60/Makefile.inc
@@ -15,3 +15,4 @@
smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c
romstage-y += dock.c
+romstage-y += gpio.c
diff --git a/src/mainboard/lenovo/t60/gpio.c b/src/mainboard/lenovo/t60/gpio.c
new file mode 100644
index 0000000000..f220b2be0c
--- /dev/null
+++ b/src/mainboard/lenovo/t60/gpio.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO, /* LEGACYIO# */
+ .gpio7 = GPIO_MODE_GPIO, /* BDC_PRESENCE# */
+ .gpio8 = GPIO_MODE_GPIO, /* H8_WAKE# */
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO, /* MDI_DETECT */
+ .gpio12 = GPIO_MODE_GPIO, /* H8SCI# */
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO, /* CPUSB# */
+ .gpio15 = GPIO_MODE_GPIO, /* CPPE# */
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO, /* MDC_KILL# */
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO, /* EXC_PWR_CTRL */
+ .gpio28 = GPIO_MODE_GPIO, /* EXC_AUX_CTRL */
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio19 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio25 = GPIO_LEVEL_HIGH,
+ .gpio26 = GPIO_LEVEL_LOW,
+ .gpio27 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio6 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio12 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio36 = GPIO_MODE_GPIO, /*PLANARID0 */
+ .gpio37 = GPIO_MODE_GPIO, /*PLANARID1 */
+ .gpio38 = GPIO_MODE_GPIO, /*PLANARID2 */
+ .gpio39 = GPIO_MODE_GPIO, /*PLANARID3 */
+ .gpio48 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio48 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+};
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index d3cd90cf65..2686635d13 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -35,41 +35,9 @@
#include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <southbridge/intel/common/gpio.h>
#include "dock.h"
-void setup_ich7_gpios(void)
-{
- printk(BIOS_DEBUG, " GPIOS...");
-
- /* T60 GPIO:
- 6: LEGACYIO#
- 7: BDC_PRESENCE#
- 8: H8_WAKE#
- 10: MDI_DETECT
- 12: H8SCI#
- 14: CPUSB#
- 15: CPPE#
- 25: MDC_KILL#
- 27: EXC_PWR_CTRL
- 28: EXC_AUX_CTRL
- 35: CLKREQ_SATA#
- 36: PLANARID0
- 37: PLANARID1
- 38: PLANARID2
- 39: PLANARID3
- */
- outl(0x1f48f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
- outl(0xe0e0ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
- outl(0xfbfefb7d, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
- /* Output Control Registers */
- outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
- /* Input Control Registers */
- outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
- outl(0x000100f0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
- outl(0x000000f1, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
- outl(0x000300a3, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
-}
-
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
@@ -224,7 +192,7 @@ void mainboard_romstage_entry(unsigned long bist)
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
/* Enable GPIOs */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10);
- setup_ich7_gpios();
+ setup_pch_gpios(&mainboard_gpio_map);
dock_err = dlpc_init();
diff --git a/src/mainboard/lenovo/x60/Makefile.inc b/src/mainboard/lenovo/x60/Makefile.inc
index 012ae7f326..bea9c2e730 100644
--- a/src/mainboard/lenovo/x60/Makefile.inc
+++ b/src/mainboard/lenovo/x60/Makefile.inc
@@ -16,3 +16,4 @@
smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c
romstage-y += dock.c
ramstage-y += dock.c
+romstage-y += gpio.c \ No newline at end of file
diff --git a/src/mainboard/lenovo/x60/gpio.c b/src/mainboard/lenovo/x60/gpio.c
new file mode 100644
index 0000000000..0498443513
--- /dev/null
+++ b/src/mainboard/lenovo/x60/gpio.c
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio1 = GPIO_MODE_GPIO, /* HDD_PRESENCE# */
+ .gpio6 = GPIO_MODE_GPIO, /* Unknown (Pulled high by R215 to VCC3B) */
+ .gpio7 = GPIO_MODE_GPIO, /* BDC_PRESENCE# */
+ .gpio8 = GPIO_MODE_GPIO, /* H8_WAKE# */
+ .gpio9 = GPIO_MODE_GPIO, /* RTC_BAT_IN# */
+ .gpio10 = GPIO_MODE_GPIO, /* Unknown (Pulled high by R700 to VCC3M) */
+ .gpio12 = GPIO_MODE_GPIO, /* H8SCI# */
+ .gpio13 = GPIO_MODE_GPIO, /* SLICE_ON_3M# */
+ .gpio14 = GPIO_MODE_GPIO, /* Unknown (Pulled high by R321 to VCC3) */
+ .gpio15 = GPIO_MODE_GPIO, /* Unknown (Pulled high by R258 to VCC3) */
+ .gpio22 = GPIO_MODE_GPIO, /* FWH_WP# */
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO, /* MDC_KILL# */
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio25 = GPIO_LEVEL_HIGH,
+ .gpio26 = GPIO_LEVEL_LOW,
+ .gpio27 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio6 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio12 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio33 = GPIO_MODE_GPIO, /* HDD_PRESENCE_2# */
+ .gpio36 = GPIO_MODE_GPIO, /* PLANARID0 */
+ .gpio37 = GPIO_MODE_GPIO, /* PLANARID1 */
+ .gpio38 = GPIO_MODE_GPIO, /* PLANARID2 */
+ .gpio39 = GPIO_MODE_GPIO, /* PLANARID3 */
+ .gpio48 = GPIO_MODE_GPIO, /* FWH_TBL# */
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio48 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+};
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 53a0151fb9..51624a009e 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -35,48 +35,9 @@
#include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <southbridge/intel/common/gpio.h>
#include "dock.h"
-void setup_ich7_gpios(void)
-{
- printk(BIOS_DEBUG, " GPIOS...");
-
- /* X60 GPIO:
- * 1: HDD_PRESENCE#
- * 6: Unknown (Pulled high by R215 to VCC3B)
- * 7: BDC_PRESENCE#
- * 8: H8_WAKE#
- * 9: RTC_BAT_IN#
- * 10: Unknown (Pulled high by R700 to VCC3M)
- * 12: H8SCI#
- * 13: SLICE_ON_3M#
- * 14: Unknown (Pulled high by R321 to VCC3)
- * 15: Unknown (Pulled high by R258 to VCC3)
- * 19: Unknown (Pulled low by R594)
- * 21: Unknown (Pulled high by R145 to VCC3)
- * 22: FWH_WP#
- * 25: MDC_KILL#
- * 33: HDD_PRESENCE_2#
- * 35: CLKREQ_SATA#
- * 36: PLANARID0
- * 37: PLANARID1
- * 38: PLANARID2
- * 39: PLANARID3
- * 48: FWH_TBL#
- */
-
- outl(0x1f40f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
- outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
- outl(0xfbf6ddfd, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
- /* Output Control Registers */
- outl(0x00040000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
- /* Input Control Registers */
- outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
- outl(0x000100f2, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
- outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
- outl(0x00030043, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
-}
-
static void ich7_enable_lpc(void)
{
// Enable Serial IRQ
@@ -222,7 +183,7 @@ void mainboard_romstage_entry(unsigned long bist)
/* Enable GPIOs */
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* 0x4c == GC */
- setup_ich7_gpios();
+ setup_pch_gpios(&mainboard_gpio_map);
ich7_enable_lpc();