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authorMichał Żygowski <michal.zygowski@3mdeb.com>2020-03-20 13:56:46 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-25 10:43:37 +0000
commit9550e97304ecc1c1b6271d50ea089c82b9a82946 (patch)
tree47d39123eae170fe1a014b8bdde8d96a17f7943c /src/mainboard/lenovo
parenta956063e5f9c19179e4bacd145e26e159f1982b2 (diff)
downloadcoreboot-9550e97304ecc1c1b6271d50ea089c82b9a82946.tar.xz
acpi: correct the processor devices scope
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here. Additionally add processor scope patching for P-State SSDT created by AGESA, becasue AGESA creates the tables with processors in \_PR scope. TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are no errors, decompile ACPI tables with acpica to check whether the processor scope is correct and if IASL does not complain on wrong checksum, run FWTS Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo')
-rw-r--r--src/mainboard/lenovo/g505s/dsdt.asl2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl
index b36a1de71d..4eb466f819 100644
--- a/src/mainboard/lenovo/g505s/dsdt.asl
+++ b/src/mainboard/lenovo/g505s/dsdt.asl
@@ -36,7 +36,7 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
- /* Describe the processor tree (\_PR) */
+ /* Describe the processor tree (\_SB) */
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */