sandy/ivy/nehalem: Remerge interrupt handling

On those chipsets the pins are just a legacy concept. Real interrupts are
messages on corresponding busses or some internal logic of chipset.
Hence interrupt routing isn't anymore board-specific (dependent on layout) but
depends only on configuration.
Rather than attempting to sync real config, ACPI and legacy descriptors, just
use the same interrupt routing per chipset covering all possible devices.

The only part which remains board-specific are LPC and PCI interrupts.

Interrupt balancing may suffer from such merge but:
a) Doesn't seem to be the case of this map on current systems
b) Almost all OS use MSI nowadays bypassing this stuff completely
c) If we want a good balancing we need to take into account that e.g.
   wlan card may be placed in a different slot and so would require complicated
   balancing on runtime. It's difficult to maintain with almost no benefit.

Change-Id: I9f63d1d338c5587ebac7a52093e5b924f6e5ca2d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7130
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

20 files changed, 4 insertions, 699 deletions

diff --git a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index b4b81a2270..0000000000
--- a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
-	If (PICM) {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, 0, 16 },//              GFX    INTA -> PIRQA (MSI)
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, 0, 16 },//  D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, 0, 17 },//  D28IP_P2IP  WLAN   INTA -> PIRQB
-			Package() { 0x001cffff, 1, 0, 21 },//  D28IP_P4IP  EXC    INTB -> PIRQF
-			Package() { 0x001cffff, 2, 0, 19 },//  D28IP_P5IP  SDCARD INTC -> PIRQD
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, 0, 19 },//  D29IP_E1P   EHCI1  INTA -> PIRQD
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, 0, 21 },//  D26IP_E2P   EHCI2  INTA -> PIRQF
-			// LPC devices			0:1f.0
-			Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP   SATA   INTA -> PIRQB (MSI)
-			Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP  SMBUS  INTB -> PIRQH
-			Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP  THRT   INTC -> PIRQA
-		})
-	} Else {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
-			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
-			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
-		})
-	}
-}
diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c
index 26a459dfaf..15b9d9a4e4 100644
--- a/src/mainboard/lenovo/t520/acpi_tables.c
+++ b/src/mainboard/lenovo/t520/acpi_tables.c
@@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
 	acpi_update_thermal_table(gnvs);
 }
 
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
-	return current;
-}
-
 unsigned long acpi_fill_slit(unsigned long current)
 {
 	// Not implemented
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index 065261a8c0..d2a4d6b9b7 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -44,15 +44,6 @@ chip northbridge/intel/sandybridge
 		device pci 02.0 on end # vga controller
 
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-			register "pirqa_routing" = "0x8b"
-			register "pirqb_routing" = "0x8a"
-			register "pirqc_routing" = "0x8b"
-			register "pirqd_routing" = "0x8b"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x80"
-
 			# GPI routing
 			#  0 No effect (default)
 			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index 83be0c7f86..f7866a86ad 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -60,48 +60,6 @@ void pch_enable_lpc(void)
 
 void rcba_config(void)
 {
-	/*
-	 *             GFX    INTA -> PIRQA (MSI)
-	 * D28IP_P2IP  WLAN   INTA -> PIRQB
-	 * D28IP_P4IP  EXC    INTB -> PIRQF
-	 * D28IP_P5IP  SDCARD INTC -> PIRQD
-	 * D29IP_E1P   EHCI1  INTA -> PIRQD
-	 * D26IP_E2P   EHCI2  INTA -> PIRQF
-	 * D31IP_SIP   SATA   INTA -> PIRQB (MSI)
-	 * D31IP_SMIP  SMBUS  INTB -> PIRQH
-	 * D31IP_TTIP  THRT   INTC -> PIRQA
-	 * D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
-	 *
-	 * Trackpad interrupt is edge triggered and cannot be shared.
-	 * TRACKPAD                -> PIRQG
-
-	 */
-
-	/* Device interrupt pin register (board specific) */
-	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
-			(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
-	RCBA32(D29IP) = (INTA << D29IP_E1P);
-	RCBA32(D28IP) = (INTA << D28IP_P2IP) | (INTB << D28IP_P4IP) |
-			(INTC << D28IP_P5IP);
-	RCBA32(D27IP) = (INTA << D27IP_ZIP);
-	RCBA32(D26IP) = (INTA << D26IP_E2P);
-	RCBA32(D25IP) = (NOINT << D25IP_LIP);
-	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
-	/* Device interrupt route registers */
-	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
-	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
-	DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
-	DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
-	DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
-	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
-	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
-	/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
-	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
-
 	/* Disable unused devices (board specific) */
 	RCBA32(FD) = 0x1ee51fe3;
 	RCBA32(BUC) = 0;
diff --git a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index 6c1c6952b8..0000000000
--- a/src/mainboard/lenovo/t530/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
-	If (PICM) {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, 0, 16 },//              GFX    INTA -> PIRQA (MSI)
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, 0, 16 },//  D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, 0, 17 },//  D28IP_P1IP  WLAN   INTA -> PIRQB
-			Package() { 0x001cffff, 1, 0, 21 },//  D28IP_P2IP  ETH0   INTB -> PIRQF
-			Package() { 0x001cffff, 2, 0, 19 },//  D28IP_P3IP  SDCARD INTC -> PIRQD
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, 0, 19 },//  D29IP_E1P   EHCI1  INTA -> PIRQD
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, 0, 21 },//  D26IP_E2P   EHCI2  INTA -> PIRQF
-			// LPC devices			0:1f.0
-			Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP   SATA   INTA -> PIRQB (MSI)
-			Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP  SMBUS  INTB -> PIRQH
-			Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP  THRT   INTC -> PIRQA
-		})
-	} Else {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
-			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
-			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
-		})
-	}
-}
diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c
index 26a459dfaf..15b9d9a4e4 100644
--- a/src/mainboard/lenovo/t530/acpi_tables.c
+++ b/src/mainboard/lenovo/t530/acpi_tables.c
@@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
 	acpi_update_thermal_table(gnvs);
 }
 
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
-	return current;
-}
-
 unsigned long acpi_fill_slit(unsigned long current)
 {
 	// Not implemented
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index ec3913c5f6..c44f927747 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -44,15 +44,6 @@ chip northbridge/intel/sandybridge
 		device pci 02.0 on end # vga controller
 
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-			register "pirqa_routing" = "0x8b"
-			register "pirqb_routing" = "0x8a"
-			register "pirqc_routing" = "0x8b"
-			register "pirqd_routing" = "0x8b"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x80"
-
 			# GPI routing
 			#  0 No effect (default)
 			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index 115f83bdbc..0a49ed05c3 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -47,48 +47,6 @@ void pch_enable_lpc(void)
 
 void rcba_config(void)
 {
-	/*
-	 *             GFX    INTA -> PIRQA (MSI)
-	 * D28IP_P1IP  WLAN   INTA -> PIRQB
-	 * D28IP_P2IP  ETH0   INTB -> PIRQF
-	 * D28IP_P3IP  SDCARD INTC -> PIRQD
-	 * D29IP_E1P   EHCI1  INTA -> PIRQD
-	 * D26IP_E2P   EHCI2  INTA -> PIRQF
-	 * D31IP_SIP   SATA   INTA -> PIRQB (MSI)
-	 * D31IP_SMIP  SMBUS  INTB -> PIRQH
-	 * D31IP_TTIP  THRT   INTC -> PIRQA
-	 * D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
-	 *
-	 * Trackpad interrupt is edge triggered and cannot be shared.
-	 * TRACKPAD                -> PIRQG
-
-	 */
-
-	/* Device interrupt pin register (board specific) */
-	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
-			(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
-	RCBA32(D29IP) = (INTA << D29IP_E1P);
-	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
-			(INTC << D28IP_P3IP);
-	RCBA32(D27IP) = (INTA << D27IP_ZIP);
-	RCBA32(D26IP) = (INTA << D26IP_E2P);
-	RCBA32(D25IP) = (NOINT << D25IP_LIP);
-	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
-	/* Device interrupt route registers */
-	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
-	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
-	DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
-	DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
-	DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
-	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
-	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
-	/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
-	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
-
 	/* Disable unused devices (board specific) */
 	RCBA32(FD) = 0x17f81fe3;
 	RCBA32(BUC) = 0;
diff --git a/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl b/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl
deleted file mode 100644
index 3e9e1b3ca7..0000000000
--- a/src/mainboard/lenovo/x201/acpi/nehalem_pci_irqs.asl
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Vladimir Serbinenko
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing.
- */
-
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
-	If (PICM) {
-		Return (Package() {
-			Package() { 0x0001ffff, 0, 0, 0x10 },
-			Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA
-			Package() { 0x0003ffff, 0, 0, 0x10 },
-			Package() { 0x0016ffff, 0, 0, 0x10 }, // ME
-			Package() { 0x0016ffff, 1, 0, 0x11 }, // ME
-			Package() { 0x0016ffff, 2, 0, 0x12 }, // ME
-			Package() { 0x0016ffff, 3, 0, 0x13 }, // ME
-			Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet
-			Package() { 0x001affff, 0, 0, 0x14 }, // USB
-			Package() { 0x001affff, 1, 0, 0x15 }, // USB
-			Package() { 0x001affff, 2, 0, 0x16 }, // USB
-			Package() { 0x001affff, 3, 0, 0x17 }, // USB
-			Package() { 0x001bffff, 1, 0, 0x11 }, // Audio
-			Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge
-			Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge
-			Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge
-			Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge
-			Package() { 0x001dffff, 0, 0, 0x10 }, // USB
-			Package() { 0x001dffff, 1, 0, 0x11 }, // USB
-			Package() { 0x001dffff, 2, 0, 0x12 }, // USB
-			Package() { 0x001dffff, 3, 0, 0x13 }, // USB
-			Package() { 0x001fffff, 0, 0, 0x17 }, // LPC
-			Package() { 0x001fffff, 1, 0, 0x10 }, // IDE
-			Package() { 0x001fffff, 2, 0, 0x11 }, // SATA
-			Package() { 0x001fffff, 3, 0, 0x13 }  // SMBUS
-		})
-	} Else {
-		Return (Package() {
-			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA
-			Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME
-			Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME
-			Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME
-			Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME
-			Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet
-			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB
-			Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB
-			Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB
-			Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB
-			Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio
-			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI
-			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI
-			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI
-			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI
-			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB
-			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB
-			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB
-			Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC
-			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE
-			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA
-			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }  // SMBus
-		})
-	}
-}
diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c
index b8979f495a..85eabc7d1f 100644
--- a/src/mainboard/lenovo/x201/acpi_tables.c
+++ b/src/mainboard/lenovo/x201/acpi_tables.c
@@ -48,42 +48,6 @@ void acpi_create_gnvs(global_nvs_t * gnvs)
 	gnvs->did[4] = 0x00000005;
 }
 
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-					   1, IO_APIC_ADDR, 0);
-
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 0, 2,
-						MP_IRQ_POLARITY_DEFAULT |
-						MP_IRQ_TRIGGER_DEFAULT);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 9, 9,
-						MP_IRQ_POLARITY_HIGH |
-						MP_IRQ_TRIGGER_LEVEL);
-
-	/* LAPIC_NMI */
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
-					      current, 0,
-					      MP_IRQ_POLARITY_HIGH |
-					      MP_IRQ_TRIGGER_EDGE, 0x01);
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
-					      current, 1, MP_IRQ_POLARITY_HIGH |
-					      MP_IRQ_TRIGGER_EDGE, 0x01);
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
-					      current, 2, MP_IRQ_POLARITY_HIGH |
-					      MP_IRQ_TRIGGER_EDGE, 0x01);
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
-					      current, 3, MP_IRQ_POLARITY_HIGH |
-					      MP_IRQ_TRIGGER_EDGE, 0x01);
-	return current;
-}
-
 unsigned long acpi_fill_slit(unsigned long current)
 {
 	/* Not implemented */
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index 614245cba9..117c25c891 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -93,15 +93,6 @@ chip northbridge/intel/nehalem
 			subsystemid 0x17aa 0x215a
 		end
 		chip southbridge/intel/ibexpeak
-			register "pirqa_routing" = "0x0b"
-			register "pirqb_routing" = "0x0b"
-			register "pirqc_routing" = "0x0b"
-			register "pirqd_routing" = "0x0b"
-			register "pirqe_routing" = "0x0b"
-			register "pirqf_routing" = "0x0b"
-			register "pirqg_routing" = "0x0b"
-			register "pirqh_routing" = "0x0b"
-
 			# GPI routing
 			#  0 No effect (default)
 			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 2c3dfd1bcc..e58f5f6d5e 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -75,41 +75,9 @@ static void pch_enable_lpc(void)
 
 static void rcba_config(void)
 {
+	southbridge_configure_default_intmap();
+
 	static const u32 rcba_dump3[] = {
-		/* 30fc */ 0x00000000,
-		/* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321,
-		/* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002,
-		/* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000,
-		/* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654,
-		/* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210,
-		/* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000,
-		/* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-		/* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 		/* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000,
 		/* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000,
 		/* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -179,8 +147,8 @@ static void rcba_config(void)
 	};
 	unsigned i;
 	for (i = 0; i < sizeof(rcba_dump3) / 4; i++) {
-		RCBA32(4 * i + 0x30fc) = rcba_dump3[i];
-		(void)RCBA32(4 * i + 0x30fc);
+		RCBA32(4 * i + 0x3310) = rcba_dump3[i];
+		(void)RCBA32(4 * i + 0x3310);
 	}
 }
 
diff --git a/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index 6c1c6952b8..0000000000
--- a/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
-	If (PICM) {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, 0, 16 },//              GFX    INTA -> PIRQA (MSI)
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, 0, 16 },//  D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, 0, 17 },//  D28IP_P1IP  WLAN   INTA -> PIRQB
-			Package() { 0x001cffff, 1, 0, 21 },//  D28IP_P2IP  ETH0   INTB -> PIRQF
-			Package() { 0x001cffff, 2, 0, 19 },//  D28IP_P3IP  SDCARD INTC -> PIRQD
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, 0, 19 },//  D29IP_E1P   EHCI1  INTA -> PIRQD
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, 0, 21 },//  D26IP_E2P   EHCI2  INTA -> PIRQF
-			// LPC devices			0:1f.0
-			Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP   SATA   INTA -> PIRQB (MSI)
-			Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP  SMBUS  INTB -> PIRQH
-			Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP  THRT   INTC -> PIRQA
-		})
-	} Else {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
-			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
-			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
-		})
-	}
-}
diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c
index 26a459dfaf..15b9d9a4e4 100644
--- a/src/mainboard/lenovo/x220/acpi_tables.c
+++ b/src/mainboard/lenovo/x220/acpi_tables.c
@@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
 	acpi_update_thermal_table(gnvs);
 }
 
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
-	return current;
-}
-
 unsigned long acpi_fill_slit(unsigned long current)
 {
 	// Not implemented
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index c1bea43e99..982e30bb09 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -48,15 +48,6 @@ chip northbridge/intel/sandybridge
 		end # vga controller
 
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-			register "pirqa_routing" = "0x8b"
-			register "pirqb_routing" = "0x8a"
-			register "pirqc_routing" = "0x8b"
-			register "pirqd_routing" = "0x8b"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x80"
-
 			# GPI routing
 			#  0 No effect (default)
 			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index ba48fac574..d9c8aa04e1 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -57,48 +57,6 @@ void pch_enable_lpc(void)
 
 void rcba_config(void)
 {
-	/*
-	 *             GFX    INTA -> PIRQA (MSI)
-	 * D28IP_P1IP  WLAN   INTA -> PIRQB
-	 * D28IP_P2IP  ETH0   INTB -> PIRQF
-	 * D28IP_P3IP  SDCARD INTC -> PIRQD
-	 * D29IP_E1P   EHCI1  INTA -> PIRQD
-	 * D26IP_E2P   EHCI2  INTA -> PIRQF
-	 * D31IP_SIP   SATA   INTA -> PIRQB (MSI)
-	 * D31IP_SMIP  SMBUS  INTB -> PIRQH
-	 * D31IP_TTIP  THRT   INTC -> PIRQA
-	 * D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
-	 *
-	 * Trackpad interrupt is edge triggered and cannot be shared.
-	 * TRACKPAD                -> PIRQG
-
-	 */
-
-	/* Device interrupt pin register (board specific) */
-	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
-			(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
-	RCBA32(D29IP) = (INTA << D29IP_E1P);
-	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
-			(INTC << D28IP_P3IP);
-	RCBA32(D27IP) = (INTA << D27IP_ZIP);
-	RCBA32(D26IP) = (INTA << D26IP_E2P);
-	RCBA32(D25IP) = (NOINT << D25IP_LIP);
-	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
-	/* Device interrupt route registers */
-	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
-	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
-	DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
-	DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
-	DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
-	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
-	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
-	/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
-	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
-
 	/* Disable unused devices (board specific) */
 	RCBA32(FD) = 0x1fe41fe3;
 	RCBA32(BUC) = 0;
diff --git a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl
deleted file mode 100644
index 6c1c6952b8..0000000000
--- a/src/mainboard/lenovo/x230/acpi/sandybridge_pci_irqs.asl
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for Sandybridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
-	If (PICM) {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, 0, 16 },//              GFX    INTA -> PIRQA (MSI)
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, 0, 16 },//  D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, 0, 17 },//  D28IP_P1IP  WLAN   INTA -> PIRQB
-			Package() { 0x001cffff, 1, 0, 21 },//  D28IP_P2IP  ETH0   INTB -> PIRQF
-			Package() { 0x001cffff, 2, 0, 19 },//  D28IP_P3IP  SDCARD INTC -> PIRQD
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, 0, 19 },//  D29IP_E1P   EHCI1  INTA -> PIRQD
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, 0, 21 },//  D26IP_E2P   EHCI2  INTA -> PIRQF
-			// LPC devices			0:1f.0
-			Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP   SATA   INTA -> PIRQB (MSI)
-			Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP  SMBUS  INTB -> PIRQH
-			Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP  THRT   INTC -> PIRQA
-		})
-	} Else {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
-			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
-			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
-		})
-	}
-}
diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c
index 26a459dfaf..15b9d9a4e4 100644
--- a/src/mainboard/lenovo/x230/acpi_tables.c
+++ b/src/mainboard/lenovo/x230/acpi_tables.c
@@ -65,24 +65,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
 	acpi_update_thermal_table(gnvs);
 }
 
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
-	return current;
-}
-
 unsigned long acpi_fill_slit(unsigned long current)
 {
 	// Not implemented
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index c44a2b7a1a..5130410e90 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -48,15 +48,6 @@ chip northbridge/intel/sandybridge
 		end # vga controller
 
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-			register "pirqa_routing" = "0x8b"
-			register "pirqb_routing" = "0x8a"
-			register "pirqc_routing" = "0x8b"
-			register "pirqd_routing" = "0x8b"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x80"
-
 			# GPI routing
 			#  0 No effect (default)
 			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 2c39741770..0bb137e732 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -60,48 +60,6 @@ void pch_enable_lpc(void)
 
 void rcba_config(void)
 {
-	/*
-	 *             GFX    INTA -> PIRQA (MSI)
-	 * D28IP_P1IP  WLAN   INTA -> PIRQB
-	 * D28IP_P2IP  ETH0   INTB -> PIRQF
-	 * D28IP_P3IP  SDCARD INTC -> PIRQD
-	 * D29IP_E1P   EHCI1  INTA -> PIRQD
-	 * D26IP_E2P   EHCI2  INTA -> PIRQF
-	 * D31IP_SIP   SATA   INTA -> PIRQB (MSI)
-	 * D31IP_SMIP  SMBUS  INTB -> PIRQH
-	 * D31IP_TTIP  THRT   INTC -> PIRQA
-	 * D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
-	 *
-	 * Trackpad interrupt is edge triggered and cannot be shared.
-	 * TRACKPAD                -> PIRQG
-
-	 */
-
-	/* Device interrupt pin register (board specific) */
-	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
-			(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
-	RCBA32(D29IP) = (INTA << D29IP_E1P);
-	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
-			(INTC << D28IP_P3IP);
-	RCBA32(D27IP) = (INTA << D27IP_ZIP);
-	RCBA32(D26IP) = (INTA << D26IP_E2P);
-	RCBA32(D25IP) = (NOINT << D25IP_LIP);
-	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
-	/* Device interrupt route registers */
-	DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
-	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
-	DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
-	DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
-	DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
-	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
-	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
-	/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
-	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
-
 	/* Disable unused devices (board specific) */
 	RCBA32(FD) = 0x17f81fe3;
 	RCBA32(BUC) = 0;