diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-08-14 08:35:11 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-08-15 03:44:46 +0200 |
| commit | a0a3727dbbd7f3ae9f9021e0797ce2fc61d1b79e (patch) | |
| tree | a0233b3d5b638eb05bf5a4d57ee64e73187da677 /src/mainboard/lenovo | |
| parent | b7f1bfcf289f218f05dfb17561a5b868eea65b92 (diff) | |
| download | coreboot-a0a3727dbbd7f3ae9f9021e0797ce2fc61d1b79e.tar.xz | |
intel/cpu: rename car.h to romstage.h
This header has nothing to do with cache-as-ram. Therefore, 'car'
is the wrong term to use. It is about providing a prototype for
*romstage*.
Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6661
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo')
| -rw-r--r-- | src/mainboard/lenovo/t520/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t530/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t60/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x201/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x230/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/romstage.c | 2 |
6 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index df460922f2..62bf1d9895 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -108,7 +108,7 @@ static void rcba_config(void) RCBA32(BUC) = 0; } -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index b2cd6163c4..8880e30e95 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -109,7 +109,7 @@ static void rcba_config(void) RCBA32(BUC) = 0; } -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 01e48e7042..f11b33e9ca 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -206,7 +206,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 5f8e291692..2c3dfd1bcc 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -215,7 +215,7 @@ static void set_fsb_frequency(void) smbus_block_write(0x69, 0, 5, block); } -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 1705003454..94fa5cf9a2 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -148,7 +148,7 @@ init_usb (void) outw (0x0000, DEFAULT_PMBASE | 0x003c); } -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> void main(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 68a9b48937..943143a506 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -213,7 +213,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> void main(unsigned long bist) { u32 reg32; |