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authorKyösti Mälkki <kyosti.malkki@gmail.com>2015-05-23 14:27:44 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-05-24 05:34:13 +0200
commit9d035fa1f7021fda52cd56aede406de7b780dfa8 (patch)
treefacbfcbbfbf835d737a6ef90128facfff2457f89 /src/mainboard/lenovo
parent7fb149dce1d13be7dfae8ec1babb000ef18d2d94 (diff)
downloadcoreboot-9d035fa1f7021fda52cd56aede406de7b780dfa8.tar.xz
AGESA binaryPI boards: Drop annoying commentary
Same comments were already removed for the latest board, the amd/lamar. Change-Id: Ie244f838409c567c11f7444c9cf17de72e49dbb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10283 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Diffstat (limited to 'src/mainboard/lenovo')
-rw-r--r--src/mainboard/lenovo/g505s/PlatformGnbPcie.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/lenovo/g505s/PlatformGnbPcie.c b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c
index b2403c1c9d..5ea0a9be8a 100644
--- a/src/mainboard/lenovo/g505s/PlatformGnbPcie.c
+++ b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c
@@ -74,48 +74,48 @@
static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */
{
- 0, /* Descriptor flags */
+ 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
{
- 0, /* Descriptor flags */
+ 0,
PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23),
PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
{
- 0, /* Descriptor flags */
+ 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
{
- 0, /* Descriptor flags */
+ 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */
{
- 0, /* Descriptor flags */
+ 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lanes 7, PCI Device Number 7, LAN */
{
- 0, /* Descriptor flags */
+ 0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
{
- DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */
+ DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
},