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| author | Nicolas Reinecke <nr@das-labor.org> | 2015-03-31 01:40:46 +0200 |
|---|---|---|
| committer | Edward O'Callaghan <edward.ocallaghan@koparo.com> | 2015-04-20 23:50:58 +0200 |
| commit | bcff3bd1b37ba11417d8643869258c83b29305b2 (patch) | |
| tree | d44501dafcc59636b3e29163a919009ee34ac0c4 /src/mainboard/lenovo | |
| parent | 59aef5c79e7ae85854a88db4803334617d7b83fd (diff) | |
| download | coreboot-bcff3bd1b37ba11417d8643869258c83b29305b2.tar.xz | |
mainboard/lenovo/t430s,t530,x230:enable usb3, set xhci overcurrent mapping
Tested on T530, T430s.
Verified with lspci dump.
Change-Id: I45acadb0c55534a67f7ad3e7bd84f4482a4344d7
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/9451
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Diffstat (limited to 'src/mainboard/lenovo')
| -rw-r--r-- | src/mainboard/lenovo/t430s/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t530/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x230/devicetree.cb | 1 |
3 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index e2ae392de3..af3de6c96d 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -67,6 +67,10 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + register "xhci_overcurrent_mapping" = "0x4000201" + # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 6b769b0397..d59524bf02 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -68,6 +68,10 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + register "xhci_overcurrent_mapping" = "0x4000201" + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 08c937f286..55677a3d7d 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -69,6 +69,7 @@ chip northbridge/intel/sandybridge register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" + register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" |