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| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-04-10 22:51:15 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-04-12 16:52:19 +0000 |
| commit | c5f1dc96bf0b18245d7986463ae56958c44d24f2 (patch) | |
| tree | ed6b20f2b323d3ff835812aa98bf9450b177c4ec /src/mainboard/libretrend | |
| parent | c1ec940eba11d279912b24377a7cf8ab4b264aaa (diff) | |
| download | coreboot-c5f1dc96bf0b18245d7986463ae56958c44d24f2.tar.xz | |
mb/*: drop LPC generic range for port 80
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have
to be set up as generic range. Drop the entries from the devicetrees.
Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/libretrend')
| -rw-r--r-- | src/mainboard/libretrend/lt1000/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 9fedde5db8..5e5c9beddf 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -28,7 +28,6 @@ chip soc/intel/skylake register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff - register "gen4_dec" = "0x000c0081" # 0x80 - 0x8f # Disable DPTF register "dptf_enable" = "0" |