mb/lippert: Unify mainboards

Do it quick and dirty but in a reproducible manner. Variants will be set
up properly in subsequent commits.

Tested with BUILD_TIMELESS=1, both Lippert FrontRunner-AF and Toucan-AF
remain identical.

Change-Id: I71ff50099787e7806a9ab67429890a1c77061929
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43274
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 54 insertions, 0 deletions

diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts-tc.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts-tc.c
new file mode 100644
index 0000000000..4861809ba6
--- /dev/null
+++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts-tc.c
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <AGESA.h>
+#include <console/console.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <SB800.h>
+#include <southbridge/amd/cimx/sb800/gpio_oem.h>
+
+/* Should AGESA_GNB_PCIE_SLOT_RESET use agesa_NoopSuccess?
+ *
+ * COM Express doesn't provide dedicated resets for individual lanes
+ * and it's not needed for the on-board Intel I210 GbE controller.
+ */
+
+static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+	{AGESA_DO_RESET,			agesa_Reset },
+	{AGESA_READ_SPD,			agesa_ReadSpd },
+	{AGESA_READ_SPD_RECOVERY,		agesa_NoopUnsupported },
+	{AGESA_RUNFUNC_ONAP,			agesa_RunFuncOnAp },
+	{AGESA_GNB_PCIE_SLOT_RESET,		agesa_NoopUnsupported },
+	{AGESA_HOOKBEFORE_DRAM_INIT,		board_BeforeDramInit },
+	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,	agesa_NoopSuccess },
+	{AGESA_HOOKBEFORE_DQS_TRAINING,		agesa_NoopSuccess },
+	{AGESA_HOOKBEFORE_EXIT_SELF_REF,	agesa_NoopSuccess },
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/*	Call the host environment interface to provide a user hook opportunity. */
+static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+{
+	MEM_DATA_STRUCT *MemData = ConfigPtr;
+
+	printk(BIOS_INFO, "Setting DDR3 voltage: ");
+	FCH_IOMUX(65) = 1; // GPIO65: VMEM_LV_EN# lowers VMEM from 1.5 to 1.35V
+	switch (MemData->ParameterListPtr->DDR3Voltage) {
+	case VOLT1_25: // board is not able to provide this
+		MemData->ParameterListPtr->DDR3Voltage = VOLT1_35; // sorry
+		printk(BIOS_INFO, "can't provide 1.25 V, using ");
+		// fall through
+	default: // AGESA.h says in mixed case 1.5V DIMMs get excluded
+	case VOLT1_35:
+		FCH_GPIO(65) = 0x08; // = output, disable PU, set to 0
+		printk(BIOS_INFO, "1.35 V\n");
+		break;
+	case VOLT1_5:
+		FCH_GPIO(65) = 0xC8; // = output, disable PU, set to 1
+		printk(BIOS_INFO, "1.5 V\n");
+	}
+
+	return AGESA_SUCCESS;
+}