LiPPERT FrontRunner-AF [2/2]: actually implement mainboard support

Step 2: change the Persimmon code to adapt it to the new board's hardware.

The FrontRunner-AF is a PC/104+ form factor embedded board:
- AMD Fusion G-T56N (1.65 GHz dual core) or T40R (1 GHz single core) APU
  - DDR3 SO-DIMM socket (1.5 or 1.35V)
  - VGA and LVDS (via Analogix ANX3110)
- AMD A55E (Hudson-E1) southbridge
  - 6x USB 2.0
  - 1x SATA, 1x CFast socket
  - HD Audio (via Realtek ALC886)
  - PCI and ISA (via ITE IT8888)
  - NEC uPD78F0532 microcontroller on I2C ("SEMA")
- Intel I210 GbE (on APU PCIe x1)
- SMSC SCH3112 SIO
  - PS/2
  - 2x RS232/485
- 2x SST 25VF032B (SO8, soldered) 4 MB SPI flash (BIOS and failsafe BIOS)

http://www.adlinktech.com/PD/web/PD_detail.php?pid=1131

Change-Id: Id55f89d224ad669b351c36128b12299802b721ba
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2553
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 22 insertions, 73 deletions

diff --git a/src/mainboard/lippert/frontrunner-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/devicetree.cb
index d108a11e5d..3a051aa87a 100644
--- a/src/mainboard/lippert/frontrunner-af/devicetree.cb
+++ b/src/mainboard/lippert/frontrunner-af/devicetree.cb
@@ -31,7 +31,7 @@ chip northbridge/amd/agesa/family14/root_complex
 						device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
 						device pci 4.0 on end # PCIE P2P bridge on-board NIC
 						device pci 5.0 off end # PCIE P2P bridge
-						device pci 6.0 on end # PCIE P2P bridge PCIe slot
+						device pci 6.0 off end # PCIE P2P bridge
 						device pci 7.0 off end # PCIE P2P bridge
 						device pci 8.0 off end # NB/SB Link P2P bridge
 					end # agesa northbridge
@@ -47,36 +47,34 @@ chip northbridge/amd/agesa/family14/root_complex
 							device i2c 50 on end
 						end
 						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
+							device i2c 51 off end
 						end
 					end # SM
-					device pci 14.1 on end # IDE	0x439c
+					device pci 14.1 off end # IDE	0x439c
 					device pci 14.2 on end # HDA	0x4383
 					device pci 14.3 on # LPC		0x439d
-					chip superio/fintek/f81865f
-						device pnp 4e.0 off		# Floppy
-							io 0x60 = 0x3f0
-							irq 0x70 = 6
-							drq 0x74 = 2
-						end
-						device pnp 4e.3 off end			# Parallel Port
-						device pnp 4e.4 off end			# Hardware Monitor
-						device pnp 4e.5 on #  Keyboard
-							io 0x60 = 0x60
-							io 0x62 = 0x64
-							irq 0x70 = 1
-						end
-						device pnp 4e.6 off end			# GPIO
-						device pnp 4e.a off end			# PME
-						device pnp 4e.10 on			# COM1
+					chip superio/smsc/smscsuperio
+						device pnp 4e.0 off end		# Floppy
+						device pnp 4e.3 off end		# Parallel Port
+						device pnp 4e.4 on		# COM1
 							io 0x60 = 0x3f8
 							irq 0x70 = 4
 						end
-						device pnp 4e.11 on			# COM2
+						device pnp 4e.5 on		# COM2
 							io 0x60 = 0x2f8
 							irq 0x70 = 3
 						end
-					end # f81865f
+						device pnp 4e.7 on		# Keyboard
+							io 0x60 = 0x60
+							io 0x62 = 0x64
+							irq 0x70 = 1
+							irq 0x72 = 12
+						end
+						device pnp 4e.A on		# Runtime Regs
+							io 0x60 = 0x0E00
+							drq 0xF0 = 0x0B # no 32kHz
+						end
+					end # smscsuperio
 				end #LPC
 				device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
 				device pci 14.5 off end # OHCI FS/LS USB
@@ -85,59 +83,10 @@ chip northbridge/amd/agesa/family14/root_complex
 				device pci 15.1 off end # PCIe PortB
 				device pci 15.2 off end # PCIe PortC
 				device pci 15.3 off end # PCIe PortD
-				device pci 16.0 off end # OHCI USB 10-13
-				device pci 16.2 off end # EHCI USB 10-13
-				register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
+				device pci 16.0 on  end # OHCI USB 10-13
+				device pci 16.2 on  end # EHCI USB 10-13
+				register "gpp_configuration" = "4" #1:1:1:1
 				register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-
-				#set up SB800 Fan control registers and IMC fan controls
-				register "imc_port_address" = "0x6E"	# 0x2E and 0x6E are common
-				register "fan0_enabled" = "1"
-				register "fan1_enabled" = "1"
-				register "imc_fan_zone0_enabled" = "1"
-				register "imc_fan_zone1_enabled" = "1"
-
-				register "fan0_config_vals" = "{ \
-					FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
-					FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\
-					0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
-				register "fan1_config_vals" = "{ \
-					FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
-					FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \
-					0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
-
-				register "imc_zone0_mode1" = " \
-					IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
-					IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0"
-				register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
-					IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
-				register "imc_zone0_temp_offset" = "0x00"	# No temp offset
-				register "imc_zone0_hysteresis" = "0x05"	# Degrees C Hysteresis
-				register "imc_zone0_smbus_addr" = "0x98"	# Temp Sensor SMBus address
-				register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3"	# SMBUS number
-				register "imc_zone0_pwm_step" = "0x01"		# Fan PWM stepping rate
-				register "imc_zone0_ramping" = "0x00"		# Disable Fan PWM ramping and stepping
-
-				register "imc_zone1_mode1" = " \
-					IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
-					IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1"
-				register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
-					IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
-				register "imc_zone1_temp_offset" = "0x00"	# No temp offset
-				register "imc_zone1_hysteresis" = "0x05"	# Degrees C Hysteresis
-				register "imc_zone1_smbus_addr" = "0x98"	# Temp Sensor SMBus address
-				register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3"	# SMBUS number
-				register "imc_zone1_pwm_step" = "0x01"		# Fan PWM stepping rate
-				register "imc_zone1_ramping" = "0x00"		# Disable Fan PWM ramping and stepping
-
-				# T56N has a Maximum operating temperature  of 90C
-				# ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C
-				# ZONEX_FANSPEEDS - Fan speeds as a "percentage"
-				register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }"
-				register "imc_zone0_fanspeeds"  = "{100,  7,  5,  4,  3, 2, 0, 0 }"
-				register "imc_zone1_thresholds" = "{ 85, 80, 75, 65,  1, 0, 0, 0, 90 }"
-				register "imc_zone1_fanspeeds"  = "{100, 10,  6,  4,  3, 0, 0, 0 }"
-
 			end	#southbridge/amd/cimx/sb800
 #			end #  device pci 18.0
 # These seem unnecessary