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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-01-08 09:32:44 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-01-16 13:19:49 +0000
commit4ebdf34e13fc3e61a6dcc60b44aa9b621a0f84ac (patch)
tree89ae271fee83032b68706cb7e044ac1960b89bb1 /src/mainboard/lippert/frontrunner-af
parent07cbd7684f13b90fc2862e8f32a2200f9d6e6e2c (diff)
downloadcoreboot-4ebdf34e13fc3e61a6dcc60b44aa9b621a0f84ac.tar.xz
AGESA fam14 boards: Clean up devicetree
Remove double nesting of chip northbridge/amd. There is requirement to keep SPD address map in the same chip block with device 0:18.2. Change-Id: Ib212f24c3d697a009d2ca8e2c77220de4bfb7573 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30733 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lippert/frontrunner-af')
-rw-r--r--src/mainboard/lippert/frontrunner-af/devicetree.cb141
1 files changed, 72 insertions, 69 deletions
diff --git a/src/mainboard/lippert/frontrunner-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/devicetree.cb
index 61a703528a..b72059a411 100644
--- a/src/mainboard/lippert/frontrunner-af/devicetree.cb
+++ b/src/mainboard/lippert/frontrunner-af/devicetree.cb
@@ -14,78 +14,80 @@
#
chip northbridge/amd/agesa/family14/root_complex
device cpu_cluster 0 on
- chip cpu/amd/agesa/family14
- device lapic 0 on end
- end
+ chip cpu/amd/agesa/family14
+ device lapic 0 on end
+ end
end
device domain 0 on
subsystemid 0x1022 0x1510 inherit
- chip northbridge/amd/agesa/family14 # CPU side of HT root complex
-# device pci 18.0 on # northbridge
- chip northbridge/amd/agesa/family14 # PCI side of HT root complex
- device pci 0.0 on end # Root Complex
- device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
- device pci 4.0 on end # PCIE P2P bridge on-board NIC
- device pci 5.0 off end # PCIE P2P bridge
- device pci 6.0 off end # PCIE P2P bridge
- device pci 7.0 off end # PCIE P2P bridge
- device pci 8.0 off end # NB/SB Link P2P bridge
- end # agesa northbridge
+ chip northbridge/amd/agesa/family14
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
+ device pci 4.0 on end # PCIE P2P bridge on-board NIC
+ device pci 5.0 off end # PCIE P2P bridge
+ device pci 6.0 off end # PCIE P2P bridge
+ device pci 7.0 off end # PCIE P2P bridge
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ end # agesa northbridge
- chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
- device pci 11.0 on end # SATA
- device pci 12.0 on end # OHCI USB 0-4
- device pci 12.2 on end # EHCI USB 0-4
- device pci 13.0 on end # OHCI USB 5-9
- device pci 13.2 on end # EHCI USB 5-9
- device pci 14.0 on # SM
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 off end
- end
- end # SM
- device pci 14.1 off end # IDE 0x439c
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC 0x439d
- chip superio/smsc/smscsuperio
- device pnp 4e.0 off end # Floppy
- device pnp 4e.3 off end # Parallel Port
- device pnp 4e.4 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 4e.5 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 4e.7 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 4e.A on # Runtime Regs
- io 0x60 = 0x0E00
- drq 0xF0 = 0x0B # no 32kHz
- end
- end # smscsuperio
- end #LPC
- device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
- device pci 14.5 off end # OHCI FS/LS USB
- device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
- device pci 15.0 off end # PCIe PortA
- device pci 15.1 off end # PCIe PortB
- device pci 15.2 off end # PCIe PortC
- device pci 15.3 off end # PCIe PortD
- device pci 16.0 on end # OHCI USB 10-13
- device pci 16.2 on end # EHCI USB 10-13
- register "gpp_configuration" = "4" #1:1:1:1
- register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
- end #southbridge/amd/cimx/sb800
-# end # device pci 18.0
-# These seem unnecessary
+ chip southbridge/amd/cimx/sb800
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # OHCI USB 0-4
+ device pci 12.2 on end # EHCI USB 0-4
+ device pci 13.0 on end # OHCI USB 5-9
+ device pci 13.2 on end # EHCI USB 5-9
+ device pci 14.0 on # SM
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 off end
+ end
+ end # SM
+ device pci 14.1 off end # IDE 0x439c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip superio/smsc/smscsuperio
+ device pnp 4e.0 off end # Floppy
+ device pnp 4e.3 off end # Parallel Port
+ device pnp 4e.4 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.5 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 4e.7 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 4e.A on # Runtime Regs
+ io 0x60 = 0x0E00
+ drq 0xF0 = 0x0B # no 32kHz
+ end
+ end # smscsuperio
+ end #LPC
+
+ device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+ device pci 14.5 off end # OHCI FS/LS USB
+ device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
+ device pci 15.0 off end # PCIe PortA
+ device pci 15.1 off end # PCIe PortB
+ device pci 15.2 off end # PCIe PortC
+ device pci 15.3 off end # PCIe PortD
+ device pci 16.0 on end # OHCI USB 10-13
+ device pci 16.2 on end # EHCI USB 10-13
+
+ register "gpp_configuration" = "4" #1:1:1:1
+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
+ end #southbridge/amd/cimx/sb800
+
+ chip northbridge/amd/agesa/family14
+
+ # These seem unnecessary
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
@@ -101,6 +103,7 @@ chip northbridge/amd/agesa/family14/root_complex
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
- end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
+ end # agesa northbridge
+
end #domain
end #northbridge/amd/agesa/family14/root_complex