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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-05-06 18:00:07 +1000 |
|---|---|---|
| committer | Rudolf Marek <r.marek@assembler.cz> | 2014-05-11 17:20:31 +0200 |
| commit | 946bee1c349db6bf88b4f6736dc910eb4890a74b (patch) | |
| tree | 2a1d672da39581017cdef0d9db528802d5202a79 /src/mainboard/lippert/literunner-lx | |
| parent | 31dbb536fae937f9201312f2c47213c65ca9d939 (diff) | |
| download | coreboot-946bee1c349db6bf88b4f6736dc910eb4890a74b.tar.xz | |
superio/ite/it8728f: RAMstage PNP configuration component
Provide devicetree.cb RAMstage configuration of this superio component.
Change-Id: I376d2fb6dafc301cbc437518012f8c43b0af4be2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5668
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Diffstat (limited to 'src/mainboard/lippert/literunner-lx')
0 files changed, 0 insertions, 0 deletions