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authorUwe Hermann <uwe@hermann-uwe.de>2008-11-19 13:42:14 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2008-11-19 13:42:14 +0000
commit86c9b8839217675cb1cc4830aa7d758864ee43f9 (patch)
tree3e66948c84653ea05bff591a34f8ac66ed414fd6 /src/mainboard/lippert/roadrunner-lx/Config.lb
parentf31ca16793ca2898e5983a12bdd706bfdd0d0efe (diff)
downloadcoreboot-86c9b8839217675cb1cc4830aa7d758864ee43f9.tar.xz
Coding-style and whitespace fixes (also to make the code more similar
the Lippert Cool SpaceRunner LX which is already in svn). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/lippert/roadrunner-lx/Config.lb')
-rw-r--r--src/mainboard/lippert/roadrunner-lx/Config.lb205
1 files changed, 104 insertions, 101 deletions
diff --git a/src/mainboard/lippert/roadrunner-lx/Config.lb b/src/mainboard/lippert/roadrunner-lx/Config.lb
index cab9aa5f72..19dd58e091 100644
--- a/src/mainboard/lippert/roadrunner-lx/Config.lb
+++ b/src/mainboard/lippert/roadrunner-lx/Config.lb
@@ -3,8 +3,6 @@
##
## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
##
-## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
-##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
@@ -20,15 +18,17 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
+
##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
default ROM_SECTION_OFFSET = 0
end
@@ -38,12 +38,12 @@ end
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
##
## Compute where this copy of coreboot will start in the boot rom
##
-default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
##
## Compute a range of ROM that can cached to speed up coreboot,
@@ -52,8 +52,8 @@ default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+default XIP_ROM_SIZE = 64 * 1024
+default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
##
@@ -73,12 +73,12 @@ if HAVE_PIRQ_TABLE
end
if USE_DCACHE_RAM
- #compile cache_as_ram.c to auto.inc
+ # compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
- depends "$(MAINBOARD)/cache_as_ram_auto.c"
- action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
- action "perl -e 's/.rodata/.rom.data/g' -pi $@"
- action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+ depends "$(MAINBOARD)/cache_as_ram_auto.c"
+ action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+ action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
@@ -136,97 +136,100 @@ if USE_DCACHE_RAM
end
##
-## Include the secondary Configuration files
+## Include the secondary configuration files
##
dir /pc80
config chip.h
-register "sio_gp1x_config" = "0x20" # bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED
+
+# Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED.
+register "sio_gp1x_config" = "0x20"
chip northbridge/amd/lx
- device pci_domain 0 on
- device pci 1.0 on end # Northbridge
- device pci 1.1 on end # Graphics
- device pci 1.2 on end # AES
- chip southbridge/amd/cs5536
- # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
- # SIRQ Mode = Active(Quiet) mode. Save power....
- # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
- register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010
- register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above
- register "lpc_serirq_mode" = "1"
- register "enable_gpio_int_route" = "0x0D0C0700"
- register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
- register "enable_USBP4_device" = "0" # 0: host, 1:device
- register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
- register "com1_enable" = "0"
- register "com1_address" = "0x3E8"
- register "com1_irq" = "6"
- register "com2_enable" = "0"
- register "com2_address" = "0x2E8"
- register "com2_irq" = "6"
- register "unwanted_vpci[0]" = "0" # End of list has a zero
- device pci 8.0 on end # Slot4
- device pci 9.0 on end # Slot3
- device pci a.0 on end # Slot2
- device pci b.0 on end # Slot1
- device pci c.0 on end # IT8888
- device pci e.0 on end # Ethernet
- device pci f.0 on # ISA Bridge
- chip superio/ite/it8712f
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 on # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 on # EC
- io 0x60 = 0x290
- io 0x62 = 0x230
- irq 0x70 = 9
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- end
- device pnp 2e.6 on # Mouse
- irq 0x70 = 12
- end
- device pnp 2e.7 on # GPIO
- io 0x62 = 0x1220
- #io 0x64 = 0x1200
- end
- device pnp 2e.8 off # MIDI
- io 0x60 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.9 off # GAME
- io 0x60 = 0x220
- end
- device pnp 2e.a off end # CIR
- end
- end
- device pci f.2 on end # IDE Controller
- device pci f.3 on end # Audio
- device pci f.4 on end # OHCI
- device pci f.5 on end # EHCI
- end
- end
- # APIC cluster is late CPU init.
- device apic_cluster 0 on
- chip cpu/amd/model_lx
- device apic 0 on end
- end
- end
+ device pci_domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ device pci 1.2 on end # AES
+ chip southbridge/amd/cs5536 # Southbridge
+ # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power...
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
+ # UARTs, etc IRQs. OK
+ register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010
+ register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above
+ register "lpc_serirq_mode" = "1"
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" # 0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x3E8"
+ register "com1_irq" = "6"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2E8"
+ register "com2_irq" = "6"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci 8.0 on end # Slot4
+ device pci 9.0 on end # Slot3
+ device pci a.0 on end # Slot2
+ device pci b.0 on end # Slot1
+ device pci c.0 on end # IT8888
+ device pci e.0 on end # Ethernet
+ device pci f.0 on # ISA bridge
+ chip superio/ite/it8712f
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # EC
+ io 0x60 = 0x290
+ io 0x62 = 0x230
+ irq 0x70 = 9
+ end
+ device pnp 2e.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x62 = 0x1220
+ # io 0x64 = 0x1200
+ end
+ device pnp 2e.8 off # MIDI
+ io 0x60 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.9 off # Game port
+ io 0x60 = 0x220
+ end
+ device pnp 2e.a off end # CIR
+ end
+ end
+ device pci f.2 on end # IDE controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+ # APIC cluster is late CPU init.
+ device apic_cluster 0 on
+ chip cpu/amd/model_lx
+ device apic 0 on end
+ end
+ end
end