newconfig is no more.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 0 insertions, 404 deletions

diff --git a/src/mainboard/lippert/roadrunner-lx/Config.lb b/src/mainboard/lippert/roadrunner-lx/Config.lb
deleted file mode 100644
index ed6d61eec0..0000000000
--- a/src/mainboard/lippert/roadrunner-lx/Config.lb
+++ /dev/null
@@ -1,198 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-	# compile cache_as_ram.c to auto.inc
-	makerule ./cache_as_ram_auto.inc
-		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		action "perl -e 's/.rodata/.rom.data/g' -pi $@"
-		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-#	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-
-	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
-	mainboardinit ./cache_as_ram_auto.inc
-
-##
-## Include the secondary configuration files
-##
-dir /pc80
-config chip.h
-
-# Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off Live LED.
-register "sio_gp1x_config" = "0x20"
-
-chip northbridge/amd/lx
-  device pci_domain 0 on
-    device pci 1.0 on end		# Northbridge
-    device pci 1.1 on end		# Graphics
-    device pci 1.2 on end		# AES
-    chip southbridge/amd/cs5536		# Southbridge
-      # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
-      # SIRQ Mode = Active(Quiet) mode. Save power...
-      # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
-      # UARTs, etc IRQs. OK
-      register "lpc_serirq_enable"        = "0x000012DA"  # 00010010 11011010
-      register "lpc_serirq_polarity"      = "0x0000ED25"  # inverse of above
-      register "lpc_serirq_mode"          = "1"
-      register "enable_gpio_int_route"    = "0x0D0C0700"
-      register "enable_ide_nand_flash"    = "0"  # 0:ide mode, 1:flash
-      register "enable_USBP4_device"      = "0"  # 0: host, 1:device
-      register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-      register "com1_enable"              = "0"
-      register "com1_address"             = "0x3E8"
-      register "com1_irq"                 = "6"
-      register "com2_enable"              = "0"
-      register "com2_address"             = "0x2E8"
-      register "com2_irq"                 = "6"
-      register "unwanted_vpci[0]"         = "0"  # End of list has a zero
-      device pci 8.0 on end		# Slot4
-      device pci 9.0 on end		# Slot3
-      device pci a.0 on end		# Slot2
-      device pci b.0 on end		# Slot1
-      device pci c.0 on end		# IT8888
-      device pci e.0 on end		# Ethernet
-      device pci f.0 on			# ISA bridge
-        chip superio/ite/it8712f
-          device pnp 2e.0 off		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on		# Com1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.2 on		# Com2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.4 on		# EC
-            io 0x60 = 0x290
-            io 0x62 = 0x230
-            irq 0x70 = 9
-          end
-          device pnp 2e.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.6 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.7 on		# GPIO
-            io 0x62 = 0x1220
-            # io 0x64 = 0x1200
-          end
-          device pnp 2e.8 off		# MIDI
-            io 0x60 = 0x300
-            irq 0x70 = 9
-          end
-          device pnp 2e.9 off		# Game port
-            io 0x60 = 0x220
-          end
-          device pnp 2e.a off end	# CIR
-        end
-      end
-      device pci f.2 on end		# IDE controller
-      device pci f.3 on end		# Audio
-      device pci f.4 on end		# OHCI
-      device pci f.5 on end		# EHCI
-    end
-  end
-  # APIC cluster is late CPU init.
-  device apic_cluster 0 on
-    chip cpu/amd/model_lx
-      device apic 0 on end
-    end
-  end
-end
diff --git a/src/mainboard/lippert/roadrunner-lx/Options.lb b/src/mainboard/lippert/roadrunner-lx/Options.lb
deleted file mode 100644
index b9ca9db796..0000000000
--- a/src/mainboard/lippert/roadrunner-lx/Options.lb
+++ /dev/null
@@ -1,206 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## Based on Options.lb from AMD's DB800 mainboard.
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESS
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEBUG
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE = 512 * 1024
-
-###
-### Build options
-###
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_VIDEO_MB = 8
-default CONFIG_PCI_ROM_RUN = 0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE = 0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET = 0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7
-default CONFIG_PIRQ_ROUTE = 1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE = 0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xc8000
-default CONFIG_DCACHE_RAM_SIZE = 0x08000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE = 8 * 1024
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE = 16 * 1024
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250 = 1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD = 115200
-#default CONFIG_TTYS0_BAUD = 57600
-#default CONFIG_TTYS0_BAUD = 38400
-#default CONFIG_TTYS0_BAUD = 19200
-#default CONFIG_TTYS0_BAUD = 9600
-#default CONFIG_TTYS0_BAUD = 4800
-#default CONFIG_TTYS0_BAUD = 2400
-#default CONFIG_TTYS0_BAUD = 1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE = 0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS = 0x3
-
-# Compile extra debugging code
-default CONFIG_DEBUG = 1
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
-
-end