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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2015-01-04 21:33:39 +1100
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2015-01-06 01:51:42 +0100
commit77757c22b9eede92234d07d65a23fdf4b970c8cf (patch)
tree29949ed8cfac9c5c9b2cf4c8071c74690411d32d /src/mainboard/lippert/toucan-af
parentd76ac6349df0147b9d8f7f09f8bb80343ecfb5e6 (diff)
downloadcoreboot-77757c22b9eede92234d07d65a23fdf4b970c8cf.tar.xz
mainboard/*/romstage.c: Sanitize system header inclusions
Fix system include paths to be consistent. Chipset support is part of the Coreboot 'system' and hence 'non-local' (i.e., in the same directory or context). One possible product of this, is to perhaps allow future work to do pre-compiled headers (PCH) on the buildbot for faster build times. However, this currently just makes mainboard's consistent. Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8085 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/lippert/toucan-af')
-rw-r--r--src/mainboard/lippert/toucan-af/romstage.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index e655f9a78a..415cdbee13 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -32,16 +32,16 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
-#include "cpu/x86/bist.h"
+#include <cpu/x86/bist.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
-#include "cpu/x86/lapic.h"
+#include <cpu/x86/lapic.h>
#include <cpu/x86/cache.h>
#include <sb_cimx.h>
#include "SBPLATFORM.h"
#include "cbmem.h"
-#include "cpu/amd/mtrr.h"
-#include "cpu/amd/agesa/s3_resume.h"
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/agesa/s3_resume.h>
#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1)