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authorStefan Reinauer <stepan@coresystems.de>2009-06-30 15:17:49 +0000
committerStefan Reinauer <stepan@openbios.org>2009-06-30 15:17:49 +0000
commit0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch)
tree81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/mainboard/lippert
parent9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff)
downloadcoreboot-0867062412dd4bfe5a556e5f3fd85ba5b682d79b.tar.xz
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/lippert')
-rw-r--r--src/mainboard/lippert/frontrunner/Config.lb26
-rw-r--r--src/mainboard/lippert/frontrunner/Options.lb132
-rw-r--r--src/mainboard/lippert/frontrunner/auto.c2
-rw-r--r--src/mainboard/lippert/roadrunner-lx/Config.lb14
-rw-r--r--src/mainboard/lippert/roadrunner-lx/Options.lb156
-rw-r--r--src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c4
-rw-r--r--src/mainboard/lippert/roadrunner-lx/irq_tables.c4
-rw-r--r--src/mainboard/lippert/spacerunner-lx/Config.lb14
-rw-r--r--src/mainboard/lippert/spacerunner-lx/Options.lb156
-rw-r--r--src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c6
-rw-r--r--src/mainboard/lippert/spacerunner-lx/irq_tables.c4
11 files changed, 259 insertions, 259 deletions
diff --git a/src/mainboard/lippert/frontrunner/Config.lb b/src/mainboard/lippert/frontrunner/Config.lb
index 4dc35b58f1..daf513380f 100644
--- a/src/mainboard/lippert/frontrunner/Config.lb
+++ b/src/mainboard/lippert/frontrunner/Config.lb
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
@@ -14,29 +14,29 @@ arch i386 end
driver mainboard.o
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
##
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+ action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
- depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+ action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
##
@@ -50,7 +50,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -72,7 +72,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
diff --git a/src/mainboard/lippert/frontrunner/Options.lb b/src/mainboard/lippert/frontrunner/Options.lb
index 70c05bfa56..eff01c1087 100644
--- a/src/mainboard/lippert/frontrunner/Options.lb
+++ b/src/mainboard/lippert/frontrunner/Options.lb
@@ -1,50 +1,50 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE = 256*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE = 256*1024
###
### Build options
@@ -53,17 +53,17 @@ default ROM_SIZE = 256*1024
##
## Build code for the fallback boot
##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
##
## no MP table
##
-default HAVE_MP_TABLE=0
+default CONFIG_HAVE_MP_TABLE=0
##
## Build code to reset the motherboard from coreboot
##
-default HAVE_HARD_RESET=0
+default CONFIG_HAVE_HARD_RESET=0
## Delay timer options
##
@@ -73,49 +73,49 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to export a programmable irq routing table
##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=2
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=2
#object irq_tables.o
##
## Build code to export a CMOS option table
##
-default HAVE_OPTION_TABLE=0
+default CONFIG_HAVE_OPTION_TABLE=0
###
### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+default CONFIG_FALLBACK_SIZE = 131072
##
## Use a small 8K stack
##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
##
## Use a small 16K heap
##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
-default CROSS_COMPILE=""
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CONFIG_CROSS_COMPILE=""
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
##
## The Serial Console
@@ -125,21 +125,21 @@ default HOSTCC="gcc"
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -151,13 +151,13 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
-## DEBUG 8 debug-level messages
+## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
#
diff --git a/src/mainboard/lippert/frontrunner/auto.c b/src/mainboard/lippert/frontrunner/auto.c
index 781fe1d0d2..3bcad1f714 100644
--- a/src/mainboard/lippert/frontrunner/auto.c
+++ b/src/mainboard/lippert/frontrunner/auto.c
@@ -84,7 +84,7 @@ static void main(unsigned long bist)
SystemPreInit();
msr_init();
- w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
diff --git a/src/mainboard/lippert/roadrunner-lx/Config.lb b/src/mainboard/lippert/roadrunner-lx/Config.lb
index 21c75d60fa..00b6713896 100644
--- a/src/mainboard/lippert/roadrunner-lx/Config.lb
+++ b/src/mainboard/lippert/roadrunner-lx/Config.lb
@@ -20,8 +20,8 @@
## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
@@ -36,14 +36,14 @@ arch i386 end
driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
# compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
- depends "$(MAINBOARD)/cache_as_ram_auto.c"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
@@ -59,7 +59,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -81,7 +81,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
# mainboardinit ./failover.inc
end
diff --git a/src/mainboard/lippert/roadrunner-lx/Options.lb b/src/mainboard/lippert/roadrunner-lx/Options.lb
index d91f602534..530c43ea78 100644
--- a/src/mainboard/lippert/roadrunner-lx/Options.lb
+++ b/src/mainboard/lippert/roadrunner-lx/Options.lb
@@ -20,69 +20,69 @@
## Based on Options.lb from AMD's DB800 mainboard.
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses CONFIG_IDE
uses CONFIG_FS_PAYLOAD
uses CONFIG_FS_EXT2
-uses AUTOBOOT_DELAY
-uses AUTOBOOT_CMDLINE
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_AUTOBOOT_DELAY
+uses CONFIG_AUTOBOOT_CMDLINE
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESS
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEBUG
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEBUG
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_VIDEO_MB
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_USE_PRINTK_IN_CAR
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE = 512 * 1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE = 512 * 1024
###
### Build options
@@ -94,17 +94,17 @@ default CONFIG_PCI_ROM_RUN = 0
##
## Build code for the fallback boot
##
-default HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_FALLBACK_BOOT = 1
##
## no MP table
##
-default HAVE_MP_TABLE = 0
+default CONFIG_HAVE_MP_TABLE = 0
##
## Build code to reset the motherboard from coreboot
##
-default HAVE_HARD_RESET = 0
+default CONFIG_HAVE_HARD_RESET = 0
## Delay timer options
##
@@ -114,57 +114,57 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
##
## Build code to export a programmable irq routing table
##
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 7
-default PIRQ_ROUTE = 1
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 7
+default CONFIG_PIRQ_ROUTE = 1
##
## Build code to export a CMOS option table
##
-default HAVE_OPTION_TABLE = 0
+default CONFIG_HAVE_OPTION_TABLE = 0
###
### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
##
## enable CACHE_AS_RAM specifics
##
-default USE_DCACHE_RAM = 1
-default DCACHE_RAM_BASE = 0xc8000
-default DCACHE_RAM_SIZE = 0x08000
+default CONFIG_USE_DCACHE_RAM = 1
+default CONFIG_DCACHE_RAM_BASE = 0xc8000
+default CONFIG_DCACHE_RAM_SIZE = 0x08000
default CONFIG_USE_PRINTK_IN_CAR=1
##
## Use a small 8K stack
##
-default STACK_SIZE = 8 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
##
## Use a small 16K heap
##
-default HEAP_SIZE = 16 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
##
## Only use the option table in a normal image
##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
##
## The Serial Console
@@ -174,24 +174,24 @@ default HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
## Select the serial console baud rate
-default TTYS0_BAUD = 115200
-#default TTYS0_BAUD = 57600
-#default TTYS0_BAUD = 38400
-#default TTYS0_BAUD = 19200
-#default TTYS0_BAUD = 9600
-#default TTYS0_BAUD = 4800
-#default TTYS0_BAUD = 2400
-#default TTYS0_BAUD = 1200
+default CONFIG_TTYS0_BAUD = 115200
+#default CONFIG_TTYS0_BAUD = 57600
+#default CONFIG_TTYS0_BAUD = 38400
+#default CONFIG_TTYS0_BAUD = 19200
+#default CONFIG_TTYS0_BAUD = 9600
+#default CONFIG_TTYS0_BAUD = 4800
+#default CONFIG_TTYS0_BAUD = 2400
+#default CONFIG_TTYS0_BAUD = 1200
# Select the serial console base port
-default TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_BASE = 0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS = 0x3
+default CONFIG_TTYS0_LCS = 0x3
# Compile extra debugging code
-default DEBUG = 1
+default CONFIG_DEBUG = 1
##
### Select the coreboot loglevel
@@ -203,13 +203,13 @@ default DEBUG = 1
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
-## DEBUG 8 debug-level messages
+## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL = 8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL = 8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
#
# CBFS
diff --git a/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c b/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c
index 660a9de02f..6a07a05e44 100644
--- a/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c
+++ b/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c
@@ -103,7 +103,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index
0x1E2C, // disable ATXPowerGood - will cause a reboot!
0x0423, // don't delay POWerOK1/2
0x9072, // watchdog triggers POWOK, counts seconds
-#if !USE_WATCHDOG_ON_BOOT
+#if !CONFIG_USE_WATCHDOG_ON_BOOT
0x0073, 0x0074, // disable watchdog by setting timeout to 0
#endif
0xBF25, 0x372A, 0xF326, // select GPIO function for most pins
@@ -149,7 +149,7 @@ void cache_as_ram_main(void)
* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
- it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter
+ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
mb_gpio_init();
uart_init();
console_init();
diff --git a/src/mainboard/lippert/roadrunner-lx/irq_tables.c b/src/mainboard/lippert/roadrunner-lx/irq_tables.c
index 4ee33d4245..0e7572da90 100644
--- a/src/mainboard/lippert/roadrunner-lx/irq_tables.c
+++ b/src/mainboard/lippert/roadrunner-lx/irq_tables.c
@@ -47,7 +47,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
- 32 + 16 * IRQ_SLOT_COUNT,/* there can be total 7 devices on the bus */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* there can be total 7 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
@@ -57,7 +57,7 @@ const struct irq_routing_table intel_irq_routing_table = {
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
- /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
+ /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
diff --git a/src/mainboard/lippert/spacerunner-lx/Config.lb b/src/mainboard/lippert/spacerunner-lx/Config.lb
index 0c2866a743..b74ce8b911 100644
--- a/src/mainboard/lippert/spacerunner-lx/Config.lb
+++ b/src/mainboard/lippert/spacerunner-lx/Config.lb
@@ -20,8 +20,8 @@
## Based on Config.lb from AMD's DB800 and DBM690T mainboards.
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
@@ -35,14 +35,14 @@ arch i386 end
driver mainboard.o
-if HAVE_PIRQ_TABLE
+if CONFIG_HAVE_PIRQ_TABLE
object irq_tables.o
end
# compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
- depends "$(MAINBOARD)/cache_as_ram_auto.c"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
@@ -58,7 +58,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -80,7 +80,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
# mainboardinit ./failover.inc
end
diff --git a/src/mainboard/lippert/spacerunner-lx/Options.lb b/src/mainboard/lippert/spacerunner-lx/Options.lb
index 5d8dd0981a..805148b7f2 100644
--- a/src/mainboard/lippert/spacerunner-lx/Options.lb
+++ b/src/mainboard/lippert/spacerunner-lx/Options.lb
@@ -20,69 +20,69 @@
## Based on Options.lb from AMD's DB800 mainboard.
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses HAVE_OPTION_TABLE
-uses USE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
uses CONFIG_ROM_PAYLOAD
uses CONFIG_IDE
uses CONFIG_FS_PAYLOAD
uses CONFIG_FS_EXT2
-uses AUTOBOOT_DELAY
-uses AUTOBOOT_CMDLINE
-uses IRQ_SLOT_COUNT
-uses MAINBOARD
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PART_NUMBER
+uses CONFIG_AUTOBOOT_DELAY
+uses CONFIG_AUTOBOOT_CMDLINE
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
-uses ARCH
-uses FALLBACK_SIZE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_ARCH
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESS
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses _RAMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_MP_TABLE
-uses CROSS_COMPILE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_RAMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_CROSS_COMPILE
uses CC
-uses HOSTCC
-uses OBJCOPY
-uses DEBUG
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_DEBUG
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_VIDEO_MB
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_USE_PRINTK_IN_CAR
-uses PIRQ_ROUTE
+uses CONFIG_PIRQ_ROUTE
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE = 512*1024
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
+default CONFIG_ROM_SIZE = 512*1024
###
### Build options
@@ -94,17 +94,17 @@ default CONFIG_PCI_ROM_RUN = 0
##
## Build code for the fallback boot
##
-default HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_FALLBACK_BOOT = 1
##
## no MP table
##
-default HAVE_MP_TABLE = 0
+default CONFIG_HAVE_MP_TABLE = 0
##
## Build code to reset the motherboard from coreboot
##
-default HAVE_HARD_RESET = 0
+default CONFIG_HAVE_HARD_RESET = 0
## Delay timer options
##
@@ -114,57 +114,57 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
##
## Build code to export a programmable irq routing table
##
-default HAVE_PIRQ_TABLE = 1
-default IRQ_SLOT_COUNT = 7
-default PIRQ_ROUTE = 1
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_IRQ_SLOT_COUNT = 7
+default CONFIG_PIRQ_ROUTE = 1
##
## Build code to export a CMOS option table
##
-default HAVE_OPTION_TABLE = 0
+default CONFIG_HAVE_OPTION_TABLE = 0
###
### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 64 * 1024
-default FALLBACK_SIZE = 128 * 1024
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_FALLBACK_SIZE = 128 * 1024
##
## enable CACHE_AS_RAM specifics
##
-default USE_DCACHE_RAM = 1
-default DCACHE_RAM_BASE = 0xc8000
-default DCACHE_RAM_SIZE = 0x08000
+default CONFIG_USE_DCACHE_RAM = 1
+default CONFIG_DCACHE_RAM_BASE = 0xc8000
+default CONFIG_DCACHE_RAM_SIZE = 0x08000
default CONFIG_USE_PRINTK_IN_CAR=1
##
## Use a small 8K stack
##
-default STACK_SIZE = 0x2000
+default CONFIG_STACK_SIZE = 0x2000
##
## Use a small 16K heap
##
-default HEAP_SIZE = 0x4000
+default CONFIG_HEAP_SIZE = 0x4000
##
## Only use the option table in a normal image
##
-#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-default USE_OPTION_TABLE = 0
+#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = 0
-default _RAMBASE = 0x00004000
+default CONFIG_RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
-default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
##
## The Serial Console
@@ -174,24 +174,24 @@ default HOSTCC = "gcc"
default CONFIG_CONSOLE_SERIAL8250 = 1
## Select the serial console baud rate
-default TTYS0_BAUD = 115200
-#default TTYS0_BAUD = 57600
-#default TTYS0_BAUD = 38400
-#default TTYS0_BAUD = 19200
-#default TTYS0_BAUD = 9600
-#default TTYS0_BAUD = 4800
-#default TTYS0_BAUD = 2400
-#default TTYS0_BAUD = 1200
+default CONFIG_TTYS0_BAUD = 115200
+#default CONFIG_TTYS0_BAUD = 57600
+#default CONFIG_TTYS0_BAUD = 38400
+#default CONFIG_TTYS0_BAUD = 19200
+#default CONFIG_TTYS0_BAUD = 9600
+#default CONFIG_TTYS0_BAUD = 4800
+#default CONFIG_TTYS0_BAUD = 2400
+#default CONFIG_TTYS0_BAUD = 1200
# Select the serial console base port
-default TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_BASE = 0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS = 0x3
+default CONFIG_TTYS0_LCS = 0x3
# Compile extra debugging code
-default DEBUG = 1
+default CONFIG_DEBUG = 1
##
### Select the coreboot loglevel
@@ -203,13 +203,13 @@ default DEBUG = 1
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
-## DEBUG 8 debug-level messages
+## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL = 8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL = 8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
#
# CBFS
diff --git a/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c b/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c
index 08be2de149..af26262387 100644
--- a/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c
+++ b/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c
@@ -89,7 +89,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
if (device != DIMM0)
return 0xFF; /* No DIMM1, don't even try. */
-#if DEBUG
+#if CONFIG_DEBUG
if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
print_err("ERROR: spd_read_byte(DIMM0, 0x");
print_err_hex8(address);
@@ -165,7 +165,7 @@ static const u16 sio_init_table[] = { // hi=data, lo=index
0x1E2C, // disable ATXPowerGood
0x0423, // don't delay POWerOK1/2
0x9072, // watchdog triggers POWOK, counts seconds
-#if !USE_WATCHDOG_ON_BOOT
+#if !CONFIG_USE_WATCHDOG_ON_BOOT
0x0073, 0x0074, // disable watchdog by setting timeout to 0
#endif
0xBF25, 0x172A, 0xF326, // select GPIO function for most pins
@@ -211,7 +211,7 @@ void cache_as_ram_main(void)
* Note: Must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
- it8712f_enable_serial(0, TTYS0_BASE); // Does not use its 1st parameter
+ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
mb_gpio_init();
uart_init();
console_init();
diff --git a/src/mainboard/lippert/spacerunner-lx/irq_tables.c b/src/mainboard/lippert/spacerunner-lx/irq_tables.c
index df2b20a969..5350b57a4d 100644
--- a/src/mainboard/lippert/spacerunner-lx/irq_tables.c
+++ b/src/mainboard/lippert/spacerunner-lx/irq_tables.c
@@ -47,7 +47,7 @@
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
- 32 + 16 * IRQ_SLOT_COUNT,/* There can be total 7 devices on the bus */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* There can be total 7 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */
@@ -57,7 +57,7 @@ const struct irq_routing_table intel_irq_routing_table = {
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
- /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
+ /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */